/external/llvm/lib/Transforms/IPO/ |
H A D | IPConstantPropagation.cpp | 250 Instruction *Ins = cast<Instruction>(*I); local 257 if (ExtractValueInst *EV = dyn_cast<ExtractValueInst>(Ins)) 270 Ins->replaceAllUsesWith(New); 271 Ins->eraseFromParent();
|
H A D | PartialInlining.cpp | 93 BasicBlock::iterator Ins = newReturnBlock->begin(); local 98 PHINode* retPhi = PHINode::Create(OldPhi->getType(), 2, "", Ins); 100 Ins = newReturnBlock->getFirstNonPHI();
|
/external/llvm/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 67 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, argument 69 unsigned NumArgs = Ins.size(); 72 MVT ArgVT = Ins[i].VT; 73 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags; 155 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument 157 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 158 MVT VT = Ins[i].VT; 159 ISD::ArgFlagsTy Flags = Ins[i].Flags;
|
H A D | RegAllocGreedy.cpp | 722 unsigned Ins = 0; local 727 BC.Entry = SpillPlacement::MustSpill, ++Ins; local 729 BC.Entry = SpillPlacement::PrefSpill, ++Ins; local 731 ++Ins; 737 BC.Exit = SpillPlacement::MustSpill, ++Ins; local 739 BC.Exit = SpillPlacement::PrefSpill, ++Ins; local 741 ++Ins; 745 if (Ins) 746 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number); 933 unsigned Ins [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.cpp | 67 &Ins, 70 unsigned NumArgs = Ins.size(); 81 EVT ArgVT = Ins[i].VT; 82 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags; 180 Hexagon_CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument 184 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 185 EVT VT = Ins[i].VT; 66 AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, Hexagon_CCAssignFn Fn, unsigned SretValueInRegs) argument
|
H A D | HexagonISelLowering.cpp | 353 SmallVectorImpl<ISD::InputArg> &Ins, 365 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon); 388 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local 432 Outs, OutVals, Ins, DAG); 596 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG, 814 SmallVectorImpl<ISD::InputArg> &Ins, 831 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon); 844 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1650 const SmallVectorImpl<ISD::InputArg> &Ins, 350 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const argument 810 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1642 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument [all...] |
/external/llvm/include/llvm/Transforms/Utils/ |
H A D | SSAUpdaterImpl.h | 71 SmallVectorImpl<PhiT*> *Ins) : 72 Updater(U), AvailableVals(A), InsertedPHIs(Ins) { } 70 SSAUpdaterImpl(UpdaterT *U, AvailableValsTy *A, SmallVectorImpl<PhiT*> *Ins) argument
|
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 548 MachineBasicBlock::iterator Ins = MBB->begin(); local 550 if (Ins != MBB->end()) 551 DL = Ins->getDebugLoc(); 558 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
|
H A D | ARMISelLowering.cpp | 1231 const SmallVectorImpl<ISD::InputArg> &Ins, 1239 CCInfo.AnalyzeCallResult(Ins, 1349 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local 1367 Outs, OutVals, Ins, DAG); 1693 if (!Ins.empty()) 1698 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1795 const SmallVectorImpl<ISD::InputArg> &Ins, 1840 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); 1845 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNod 1229 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1788 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument 2666 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.h | 91 Ins, enumerator in enum:llvm::MipsISD::NodeType 228 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, 232 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, 307 const SmallVectorImpl<ISD::InputArg> &Ins, 374 const SmallVectorImpl<ISD::InputArg> &Ins,
|
H A D | MipsISelLowering.cpp | 172 case MipsISD::Ins: return "MipsISD::Ins"; 814 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0), 1818 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1862 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1909 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 1934 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 2589 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local 2775 Ins, D 2781 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SDNode *CallNode, const Type *RetTy) const argument 2819 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3477 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat, const SDNode *CallNode, const Type *RetTy) const argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 84 const SmallVectorImpl<ISD::InputArg> &Ins, 99 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) { 100 const ISD::InputArg &Arg = Ins[i]; 152 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) { 179 const ISD::InputArg &Arg = Ins[i]; 80 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
|
H A D | R600ISelLowering.cpp | 937 const SmallVectorImpl<ISD::InputArg> &Ins, 943 for (unsigned i = 0, e = Ins.size(); i < e; ++i, ++FuncArg) { 944 EVT VT = Ins[i].VT; 933 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
|
/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.cpp | 692 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local 833 if (!Ins.empty()) 839 Ins, dl, DAG, InVals); 846 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, 854 CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze); 876 const SmallVectorImpl<ISD::InputArg> &Ins, 897 CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze); 1002 // the size of Ins and InVals. This only happens when on varg functions 845 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 875 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
|
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 256 &Ins, 267 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 269 if (Ins.empty()) 282 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local 298 Outs, OutVals, Ins, dl, DAG, InVals); 312 &Ins, 326 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430); 373 ISD::ArgFlagsTy Flags = Ins[i].Flags; 465 const SmallVectorImpl<ISD::InputArg> &Ins, 252 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 308 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 459 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 599 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 148 &Ins, 161 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); 168 if (i == 0 && Ins[i].Flags.isSRet()) { 351 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local 597 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); 145 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
|
/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.h | 76 std::pair<CompMap::iterator, bool> Ins = local 78 return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second;
|
H A D | CodeGenRegisters.cpp | 316 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins = local 318 if (Ins->second == SI->first) 326 SI->first->getName() + " and " + Ins->second->getName());
|
/external/llvm/include/llvm/TableGen/ |
H A D | Record.h | 1672 bool Ins = Classes.insert(std::make_pair(R->getName(), R)).second; local 1673 (void)Ins; 1674 assert(Ins && "Class already exists"); 1677 bool Ins = Defs.insert(std::make_pair(R->getName(), R)).second; local 1678 (void)Ins; 1679 assert(Ins && "Record already exists");
|
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 417 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local 574 if (Ins.size() > 0) { 668 DAG.getConstant(isABI ? ((Ins.size()==0) ? 0 : 1) 719 if (Ins.size() > 0) { 722 for (unsigned i=0,e=Ins.size(); i!=e; ++i) { 723 unsigned sz = Ins[i].VT.getSizeInBits(); 724 if (Ins[i].VT.isInteger() && (sz < 8)) sz = 8; 725 EVT LoadRetVTs[] = { Ins[i].VT, MVT::Other, MVT::Glue }; 744 assert(Ins 1037 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 1986 SmallVector<ISD::InputArg, 32> Ins; local 2003 Ins.push_back(MyFlags); 2013 CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86);
|
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 901 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local 919 Outs, OutVals, Ins, dl, DAG, InVals); 933 const SmallVectorImpl<ISD::InputArg> &Ins, 1048 Ins, dl, DAG, InVals); 1056 const SmallVectorImpl<ISD::InputArg> &Ins, 1065 CCInfo.AnalyzeCallResult(Ins, RetCC_XCore); 1087 const SmallVectorImpl<ISD::InputArg> &Ins, 1099 Ins, dl, DAG, InVals); 1112 &Ins, 928 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1054 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1084 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1108 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 894 const SmallVectorImpl<ISD::InputArg> &Ins, 906 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); 913 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1086 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local 1103 Outs, OutVals, Ins, DAG); 1339 IsVarArg, Ins, dl, DAG, InVals); 1345 const SmallVectorImpl<ISD::InputArg> &Ins, 1352 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForNode(CallConv)); 1395 const SmallVectorImpl<ISD::InputArg> &Ins, 892 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1343 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1388 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg, bool IsCalleeStructRet, bool IsCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 6466 CLI.Ins.clear(); 6483 CLI.Ins.push_back(MyFlags); 6495 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && 6507 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { 6510 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && 6597 SmallVector<ISD::InputArg, 16> Ins; local 6610 Ins.push_back(RetArg); 6664 Ins.push_back(MyFlags); 6672 F.isVarArg(), Ins, 6678 assert(InVals.size() == Ins [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1849 &Ins, 1855 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, 1858 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, 1861 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1871 &Ins, 1922 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4); 1983 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal); 2131 &Ins, 2176 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 2179 EVT ObjectVT = Ins[ArgN 1846 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1867 LowerFormalArguments_32SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2127 LowerFormalArguments_64SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2416 LowerFormalArguments_Darwin( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2855 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument 3276 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3322 FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall, bool isVarArg, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag, SDValue Chain, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals) const argument 3424 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local 3452 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3684 LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 4055 LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument [all...] |