/external/llvm/lib/CodeGen/ |
H A D | LiveVariables.cpp | 182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { argument 183 VarInfo &VRInfo = getVarInfo(Reg); 192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, argument 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 219 if (TRI->isSubRegister(Reg, DefReg)) { 231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { argument 232 MachineInstr *LastDef = PhysRegDef[Reg]; 234 if (!LastDef && !PhysRegUse[Reg]) { 242 // All of the sub-registers must have been defined before the use of Reg! 244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefReg 281 FindLastRefOrPartRef(unsigned Reg) argument 311 HandlePhysRegKill(unsigned Reg, MachineInstr *MI) argument 443 HandlePhysRegDef(unsigned Reg, MachineInstr *MI, SmallVector<unsigned, 4> &Defs) argument 489 unsigned Reg = Defs.back(); local 652 const unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local 677 replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, MachineInstr *NewMI) argument 690 unsigned Reg = MO.getReg(); local 715 isLiveIn(const MachineBasicBlock &MBB, unsigned Reg, MachineRegisterInfo &MRI) argument 733 isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) argument 814 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local [all...] |
H A D | MachineCSE.cpp | 81 bool isPhysDefTriviallyDead(unsigned Reg, 94 bool isProfitableToCSE(unsigned CSReg, unsigned Reg, 121 unsigned Reg = MO.getReg(); local 122 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 124 if (!MRI->hasOneNonDBGUse(Reg)) 128 MachineInstr *DefMI = MRI->getVRegDef(Reg); 136 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg))) 151 MachineCSE::isPhysDefTriviallyDead(unsigned Reg, argument 167 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) 171 if (!TRI->regsOverlap(MO.getReg(), Reg)) 203 unsigned Reg = MO.getReg(); local 222 unsigned Reg = MO.getReg(); local 341 isProfitableToCSE(unsigned CSReg, unsigned Reg, MachineInstr *CSMI, MachineInstr *MI) argument [all...] |
H A D | RegAllocFast.cpp | 202 // Find the location Reg would belong... 702 unsigned Reg = MO.getReg(); local 703 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 706 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { 707 if (ThroughRegs.insert(Reg)) 708 DEBUG(dbgs() << ' ' << PrintReg(Reg)); 718 unsigned Reg = MO.getReg(); local 719 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 720 markRegUsedInInstr(Reg); 732 unsigned Reg = MO.getReg(); local 757 unsigned Reg = MO.getReg(); local 773 unsigned Reg = MO.getReg(); local 848 unsigned Reg = MO.getReg(); local 918 unsigned Reg = MO.getReg(); local 968 unsigned Reg = MO.getReg(); local 990 unsigned Reg = MO.getReg(); local 1019 unsigned Reg = MO.getReg(); local [all...] |
H A D | RegAllocGreedy.cpp | 148 unsigned Reg = (*Begin)->reg; local 149 if (ExtraRegInfo[Reg].Stage == RS_New) 150 ExtraRegInfo[Reg].Stage = NewStage; 193 void reset(InterferenceCache &Cache, unsigned Reg) { argument 194 PhysReg = Reg; 196 Intf.setPhysReg(Cache, Reg); 396 const unsigned Reg = LI->reg; local 397 assert(TargetRegisterInfo::isVirtualRegister(Reg) && 401 ExtraRegInfo.grow(Reg); 402 if (ExtraRegInfo[Reg] [all...] |
H A D | RegAllocPBQP.cpp | 203 for (unsigned Reg = 1, e = tri->getNumRegs(); Reg != e; ++Reg) { 204 if (mri->def_empty(Reg)) 206 pregs.insert(Reg); 207 mri->setPhysRegUsed(Reg); 452 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local 453 if (mri->reg_nodbg_empty(Reg)) 455 LiveInterval *li = &lis->getInterval(Reg);
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H A D | RegisterPressure.cpp | 49 void RegisterPressure::increase(unsigned Reg, const TargetRegisterInfo *TRI, argument 51 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 52 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 59 TRI->getRegUnitPressureSets(Reg), 60 TRI->getRegUnitWeight(Reg)); 65 void RegisterPressure::decrease(unsigned Reg, const TargetRegisterInfo *TRI, argument 67 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 68 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 73 decreaseSetPressure(MaxSetPressure, TRI->getRegUnitPressureSets(Reg), 74 TRI->getRegUnitWeight(Reg)); 308 containsReg(ArrayRef<unsigned> Regs, unsigned Reg) argument 341 pushRegUnits(unsigned Reg, SmallVectorImpl<unsigned> &Regs) argument 379 discoverLiveIn(unsigned Reg) argument 390 discoverLiveOut(unsigned Reg) argument 441 unsigned Reg = RegOpers.Defs[i]; local 450 unsigned Reg = RegOpers.Uses[i]; local 491 unsigned Reg = RegOpers.Uses[i]; local 516 unsigned Reg = RegOpers.Defs[i]; local 627 unsigned Reg = RegOpers.Defs[i]; local 633 unsigned Reg = RegOpers.Uses[i]; local 674 findUseBetween(unsigned Reg, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo *MRI, const LiveIntervals *LIS) argument 711 unsigned Reg = RegOpers.Uses[i]; local [all...] |
H A D | ShrinkWrapping.cpp | 412 unsigned Reg = CSI[inx].getReg(); local 413 // If instruction I reads or modifies Reg, add it to UsedCSRegs, 423 if (MOReg == Reg || 425 TargetRegisterInfo::isPhysicalRegister(Reg) && 426 TRI->isSubRegister(Reg, MOReg))) { 427 // CSR Reg is defined/used in block MBB.
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H A D | StrongPHIElimination.cpp | 139 // Merges the live interval of Reg into NewReg and renames Reg to NewReg 140 // everywhere that Reg appears. Requires Reg and NewReg to have non- 142 void MergeLIsAndRename(unsigned Reg, unsigned NewReg); 217 static MachineOperand *findLastUse(MachineBasicBlock *MBB, unsigned Reg) { argument 227 if (MO.isReg() && MO.isUse() && MO.getReg() == Reg) 406 void StrongPHIElimination::addReg(unsigned Reg) { argument 407 Node *&N = RegNodeMap[Reg]; 409 N = new (Allocator) Node(Reg); 428 getRegColor(unsigned Reg) argument 452 isolateReg(unsigned Reg) argument 797 MergeLIsAndRename(unsigned Reg, unsigned NewReg) argument [all...] |
H A D | TailDuplication.cpp | 329 static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB, argument 331 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), 429 unsigned Reg = MO.getReg(); local 430 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 433 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 436 LocalVRMap.insert(std::make_pair(Reg, NewReg)); 437 if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg)) 438 AddSSAUpdateEntry(Reg, NewReg, PredBB); 440 DenseMap<unsigned, unsigned>::iterator VI = LocalVRMap.find(Reg); 476 unsigned Reg = MO0.getReg(); local [all...] |
H A D | TargetInstrInfo.cpp | 481 unsigned Reg = MO.getReg(); local 482 if (Reg == 0) 486 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 491 if (!MRI.isConstantPhysReg(Reg, MF)) 502 if (MO.isDef() && Reg != DefReg)
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGFast.cpp | 387 void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, argument 417 SDep FromDep(SU, SDep::Data, Reg); 433 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, argument 439 if (Reg == *ImpDef) 448 static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg, argument 454 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 502 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); local 503 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 504 CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI); 516 for (const uint16_t *Reg 572 unsigned Reg = LRegs[0]; local [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 375 unsigned Reg = Op.getReg(); local 376 O << getRegisterName(Reg);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 167 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { argument 168 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 214 unsigned Reg = Order[I]; local 215 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 218 unsigned Paired = getPairedGPR(Reg, !Odd, this); 221 Hints.push_back(Reg); 226 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, argument 229 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 233 // If 'Reg' i [all...] |
H A D | ARMExpandPseudoInsts.cpp | 350 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, argument 354 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 355 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 356 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 357 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 359 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 360 D1 = TRI->getSubReg(Reg, ARM::dsub_2); 361 D2 = TRI->getSubReg(Reg, ARM::dsub_4); 362 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 365 D0 = TRI->getSubReg(Reg, AR [all...] |
H A D | ARMMachineFunctionInfo.h | 258 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
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H A D | Thumb2SizeReduction.cpp | 244 unsigned Reg = MO.getReg(); local 245 if (Reg == 0 || Reg == ARM::CPSR) 247 Defs.insert(Reg); 254 unsigned Reg = MO.getReg(); local 255 if (Defs.count(Reg)) 317 unsigned Reg = MO.getReg(); local 318 if (Reg == 0 || Reg == ARM::CPSR) 320 if (isPCOk && Reg 744 unsigned Reg = MO.getReg(); local [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 264 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg(); local 265 if (MRC.contains(Reg)) { 272 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0, 292 unsigned Reg = Op.getReg(); local 293 printRegName(O, Reg); 724 unsigned Reg = MI->getOperand(OpNum).getReg(); local 725 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0)); 727 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1)); 1016 unsigned Reg = MO1.getReg(); local 1017 printRegName(O, Reg); [all...] |
/external/llvm/lib/Target/MBlaze/AsmParser/ |
H A D | MBlazeAsmParser.cpp | 110 struct RegOp Reg; member in union:__anon9711::MBlazeOperand::__anon9712 124 Reg = o.Reg; 149 return Reg.RegNum; 238 Op->Reg.RegNum = RegNum; 393 MBlazeOperand *Reg = ParseRegister(StartLoc, EndLoc); local 394 if (!Reg) 396 RegNo = Reg->getReg();
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/external/llvm/lib/Target/Mips/ |
H A D | MipsDelaySlotFiller.cpp | 101 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg, 104 /// Returns true if Reg or its alias is in RegSet. 105 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const; 370 unsigned Reg, bool IsDef) const { 372 NewDefs.set(Reg); 373 // check whether Reg has already been defined or used. 374 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg)); 377 NewUses.set(Reg); 378 // check whether Reg ha 369 checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg, bool IsDef) const argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCCTRLoops.cpp | 517 unsigned Reg = MO.getReg(); local 518 if (!MRI->use_nodbg_empty(Reg)) { 523 MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg); 575 unsigned Reg = MO.getReg(); local 577 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | R600MCCodeEmitter.cpp | 312 unsigned Reg = RegMO.getReg(); local 313 if (Reg == AMDGPU::ALU_CONST) { 322 if (Reg == AMDGPU::ALU_LITERAL_X) {
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/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 162 unsigned Reg = VA.getLocReg(); local 167 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0, 169 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass); 170 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT)); 174 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); 176 Reg = MF.addLiveIn(Reg, RC); 177 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, V 506 RegisterSDNode *Reg = cast<RegisterSDNode>(Node->getOperand(1).getNode()); local [all...] |
/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 751 unsigned Reg = MO.getReg(); local 752 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
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/external/llvm/utils/TableGen/ |
H A D | DAGISelMatcherGen.cpp | 29 const CodeGenRegister *Reg = T.getRegBank().getReg(R); local 34 if (!RC.contains(Reg)) 581 const CodeGenRegister *Reg = local 583 AddMatcher(new EmitRegisterMatcher(Reg, N->getType(0))); 787 Record *Reg = Pattern.getDstRegs()[i]; local 788 if (!Reg->isSubClassOf("Register") || Reg == HandledReg) continue; 789 ResultVTs.push_back(getRegisterValueType(Reg, CGT)); 913 Record *Reg = Pattern.getDstRegs()[i]; local 914 if (!Reg [all...] |
H A D | RegisterInfoEmitter.cpp | 320 Record *Reg = Regs[i]->TheDef; local 321 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 323 if (DwarfRegNums.count(Reg)) 324 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 325 getQualifiedName(Reg) + "specified multiple times"); 326 DwarfRegNums[Reg] = RegNums; 387 Record *Reg = Regs[i]->TheDef; local 388 const RecordVal *V = Reg->getValue("DwarfAlias"); 394 DwarfRegNums[Reg] = DwarfRegNums[Alias]; 443 Record *Reg local 728 const CodeGenRegister *Reg = Regs[i]; local 815 const CodeGenRegister *Reg = Regs[i]; local 857 Record *Reg = Order[i]; local 867 Record *Reg = Order[i]; local 910 Record *Reg = Regs[i]->TheDef; local 1210 const CodeGenRegister &Reg = *Regs[i]; local [all...] |