Searched defs:Reg (Results 51 - 75 of 193) sorted by relevance

12345678

/external/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp119 unsigned Reg = CSI[i].getReg(); local
121 switch (Reg) {
127 if (Reg == FramePtr)
136 if (Reg == FramePtr)
215 static bool isCalleeSavedRegister(unsigned Reg, const uint16_t *CSRegs) { argument
217 if (Reg == CSRegs[i])
345 unsigned Reg = CSI[i-1].getReg(); local
351 if (Reg == ARM::LR) {
354 MF.getRegInfo().isLiveIn(Reg))
359 MBB.addLiveIn(Reg);
386 unsigned Reg = CSI[i-1].getReg(); local
[all...]
H A DThumb2ITBlockPass.cpp65 unsigned Reg = MO.getReg(); local
66 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
69 LocalUses.push_back(Reg);
71 LocalDefs.push_back(Reg);
75 unsigned Reg = LocalUses[i]; local
76 Uses.insert(Reg);
77 for (MCSubRegIterator Subreg(Reg, TRI); Subreg.isValid(); ++Subreg)
82 unsigned Reg local
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp214 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) { argument
215 MCSuperRegIterator SRI(Reg, TRI);
244 unsigned Reg = CSI[i].getReg(); local
249 unsigned SuperReg = uniqueSuperReg(Reg, TRI);
268 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
269 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RC,
271 MBB.addLiveIn(Reg);
299 unsigned Reg = CSI[i].getReg(); local
304 unsigned SuperReg = uniqueSuperReg(Reg, TRI);
322 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
[all...]
H A DHexagonNewValueJump.cpp135 unsigned Reg = II->getOperand(i).getReg(); local
140 if (localBegin->modifiesRegister(Reg, TRI) ||
141 localBegin->readsRegister(Reg, TRI))
/external/llvm/lib/Target/MBlaze/
H A DMBlazeAsmPrinter.cpp136 unsigned Reg = CSI[i].getReg(); local
137 unsigned RegNum = getMBlazeRegisterNumbering(Reg);
138 if (MBlaze::GPRRegClass.contains(Reg))
H A DMBlazeMachineFunction.h158 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
161 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp42 SDValue Reg; member in struct:__anon9724::MSP430ISelAddressMode::__anon9726
65 if (BaseType == RegBase && Base.Reg.getNode() != 0) {
66 errs() << "Base.Reg ";
67 Base.Reg.getNode()->dump();
173 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
180 AM.Base.Reg = N;
202 && AM.Base.Reg.getNode() == 0) {
257 if (!AM.Base.Reg.getNode())
258 AM.Base.Reg = CurDAG->getRegister(0, VT);
263 AM.Base.Reg;
[all...]
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp199 unsigned Reg = MO.getReg(); local
200 unsigned RegNo = Ctx.getRegisterInfo().getEncodingValue(Reg);
/external/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp329 unsigned Reg =0; local
340 Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
341 if (Reg == 0) {
342 FirstRegSaved = Reg = Mips::V0;
347 rs.setUsed(Reg);
348 BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
349 BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
354 if (Reg != Mips::V1) {
368 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg)
[all...]
H A DMipsSEFrameLowering.cpp96 unsigned Reg = I->getReg(); local
98 // If Reg is a double precision register, emit two cfa_offsets,
100 if (Mips::AFGR64RegClass.contains(Reg)) {
103 MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
104 MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd));
112 // Reg is either in CPURegs or FGR32.
114 SrcML = MachineLocation(Reg);
227 unsigned Reg = CSI[i].getReg(); local
228 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg
[all...]
H A DMipsSEInstrInfo.cpp91 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
103 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
121 else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
131 else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
267 unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0); local
268 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
297 unsigned Reg = RegInfo.createVirtualRegister(RC); local
300 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
302 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
307 BuildMI(MBB, II, DL, get(Inst->Opc), Reg)
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp498 unsigned Reg = 0; local
501 Reg = PPC::CR0;
504 Reg = PPC::CR1;
507 Reg = PPC::CR2;
510 Reg = PPC::CR3;
513 Reg = PPC::CR4;
516 Reg = PPC::CR5;
519 Reg = PPC::CR6;
522 Reg = PPC::CR7;
524 return StoreRegToStackSlot(MF, Reg, isKil
608 unsigned Reg = 0; local
[all...]
H A DPPCRegisterInfo.cpp210 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); local
213 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
217 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
221 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
230 .addReg(Reg, RegState::Kill)
245 .addReg(Reg, RegState::Kill)
289 unsigned Reg = LP64 ? PPC::X0 : PPC::R0; local
294 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg)
301 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
302 .addReg(Reg, RegStat
331 unsigned Reg = LP64 ? PPC::X0 : PPC::R0; local
357 hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const argument
[all...]
/external/llvm/lib/Target/R600/
H A DAMDGPUIndirectAddressing.cpp37 bool regHasExplicitDef(MachineRegisterInfo &MRI, unsigned Reg) const;
166 unsigned Reg = *LJ; local
167 if (RegisterAddressMap.find(Reg) == RegisterAddressMap.end()) {
171 if (RegisterAddressMap[Reg] == Address) {
172 PhiRegisters.push_back(Reg);
194 unsigned Reg = *RI; local
195 MachineInstr *DefInst = MRI.getVRegDef(Reg);
198 Phi.addReg(Reg);
200 MBB.removeLiveIn(Reg);
223 unsigned Reg local
252 unsigned Reg = LiveAddressRegisterMap[Address]; local
288 unsigned Reg = LiveAddressRegisterMap[Addr]; local
[all...]
H A DAMDGPUInstrInfo.cpp166 unsigned Reg, bool UnfoldLoad,
165 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
H A DR600MachineScheduler.cpp176 bool R600SchedStrategy::regBelongsToClass(unsigned Reg, argument
178 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
179 return RC->contains(Reg);
181 return MRI->getRegClass(Reg) == RC;
H A DSIInsertWaits.cpp139 unsigned Reg = Op.getReg(); local
140 unsigned Size = TRI.getMinimalPhysRegClass(Reg)->getSize();
184 unsigned Reg = Op.getReg(); local
185 unsigned Size = TRI.getMinimalPhysRegClass(Reg)->getSize();
190 Result.first = TRI.getEncodingValue(Reg);
H A DSILowerControlFlow.cpp179 unsigned Reg = MI.getOperand(0).getReg(); local
182 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
185 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
187 .addReg(Reg);
275 unsigned Reg = MI.getOperand(0).getReg(); local
280 .addReg(Reg);
/external/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp243 unsigned Reg = MO.getReg(); local
248 Reg = getX86SubSuperRegister(Reg, VT);
250 O << X86ATTInstPrinter::getRegisterName(Reg);
381 unsigned Reg = MO.getReg(); local
385 Reg = getX86SubSuperRegister(Reg, MVT::i8);
388 Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
391 Reg
[all...]
H A DX86CodeEmitter.cpp187 unsigned Reg = MO.getReg(); local
188 if (X86II::isX86_64NonExtLowByteReg(Reg))
H A DX86InstrBuilder.h44 unsigned Reg; member in union:llvm::X86AddressMode::__anon9837
56 Base.Reg = 0;
64 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument
92 // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
103 /// [Reg + Offset], i.e., one with no scale or index, but with a
108 unsigned Reg, bool isKill, int Offset) {
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
113 /// [Reg
107 addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset) argument
[all...]
H A DX86MachineFunctionInfo.h118 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
121 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
H A DX86RegisterInfo.cpp444 unsigned Reg, int &FrameIdx) const {
447 if (Reg == FramePtr && TFI->hasFP(MF)) {
519 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT, argument
525 switch (Reg) {
526 default: return getX86SubSuperRegister(Reg, MVT::i64);
545 switch (Reg) {
582 switch (Reg) {
618 switch (Reg) {
654 switch (Reg) {
443 hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const argument
/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp202 unsigned Reg = CSI.getReg(); local
204 MachineLocation CSSrc(Reg);
291 unsigned Reg = it->getReg(); local
292 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
293 TII.storeRegToStackSlot(MBB, MI, Reg, true,
317 unsigned Reg = it->getReg(); local
318 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
H A DXCoreRegisterInfo.cpp152 unsigned Reg = MI.getOperand(0).getReg(); local
155 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
171 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
177 .addReg(Reg, getKillRegState(isKill))
182 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
192 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
198 .addReg(Reg, getKillRegState(isKill))
203 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
221 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
227 .addReg(Reg, getKillRegStat
[all...]

Completed in 394 milliseconds

12345678