/external/llvm/lib/CodeGen/ |
H A D | LiveRegMatrix.cpp | 50 TRI = MF.getTarget().getRegisterInfo(); 55 unsigned NumRegUnits = TRI->getNumRegUnits(); 73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) 74 << " to " << PrintReg(PhysReg, TRI) << ':'); 78 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 79 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI)); 88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) 89 << " from " << PrintReg(PhysReg, TRI) << ':'); 91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 92 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI)); [all...] |
H A D | AllocationOrder.cpp | 34 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); local 36 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM); 43 dbgs() << ' ' << PrintReg(Hints[I], TRI);
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H A D | RegisterCoalescer.h | 29 const TargetRegisterInfo &TRI; member in class:llvm::CoalescerPair 63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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H A D | RegisterClassInfo.cpp | 32 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0) 40 if (MF->getTarget().getRegisterInfo() != TRI) { 41 TRI = MF->getTarget().getRegisterInfo(); 42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 47 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); 52 CSRNum.resize(TRI->getNumRegs(), 0); 54 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 98 unsigned Cost = TRI->getCostPerUse(PhysReg); 117 unsigned Cost = TRI->getCostPerUse(PhysReg); 129 if (const TargetRegisterClass *Super = TRI [all...] |
H A D | RegisterScavenging.cpp | 36 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 41 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 73 TRI = TM.getRegisterInfo(); 76 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) && 86 NumPhysRegs = TRI->getNumRegs(); 93 const uint16_t *CSRegs = TRI->getCalleeSavedRegs(&MF); 107 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 188 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 205 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && 230 DEBUG(dbgs() << "Scavenger found unused reg: " << TRI [all...] |
H A D | MachineRegisterInfo.cpp | 20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) argument 21 : TRI(&TRI), IsSSA(true), TracksLiveness(true) { 24 UsedRegUnits.resize(TRI.getNumRegUnits()); 25 UsedPhysRegMask.resize(TRI.getNumRegs()); 28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 51 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 64 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); 74 I->getRegClassConstraint(I.getOperandNo(), TII, TRI); 308 EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) argument [all...] |
H A D | TargetRegisterInfo.cpp | 41 else if (TRI && Reg < TRI->getNumRegs()) 42 OS << '%' << TRI->getName(Reg); 46 if (TRI) 47 OS << ':' << TRI->getSubRegIndexName(SubIdx); 54 // Generic printout when TRI is missing. 55 if (!TRI) { 61 if (Unit >= TRI->getNumRegUnits()) { 67 MCRegUnitRootIterator Roots(Unit, TRI); 69 OS << TRI 151 firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI) argument [all...] |
H A D | RegAllocBase.h | 61 const TargetRegisterInfo *TRI; member in class:llvm::RegAllocBase 68 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
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H A D | MachineCopyPropagation.cpp | 35 const TargetRegisterInfo *TRI; member in class:__anon9475::MachineCopyPropagation 68 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 77 for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR) 114 const TargetRegisterInfo *TRI) { 118 if (TRI->isSubRegister(SrcSrc, Def)) { 120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); 123 return SubIdx == TRI->getSubRegIndex(SrcDef, Src); 164 isNopCopy(CopyMI, Def, Src, TRI)) { 182 I->clearRegisterKills(Def, TRI); 192 for (MCRegAliasIterator AI(Src, TRI, tru 113 isNopCopy(MachineInstr *CopyMI, unsigned Def, unsigned Src, const TargetRegisterInfo *TRI) argument [all...] |
H A D | InterferenceCache.h | 25 const TargetRegisterInfo *TRI; member in class:llvm::InterferenceCache 112 void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI); 115 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI); 120 const TargetRegisterInfo *TRI, 150 InterferenceCache() : TRI(0), LIUArray(0), MF(0), RoundRobin(0) {}
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H A D | AggressiveAntiDepBreaker.cpp | 122 TRI(MF.getTarget().getRegisterInfo()), 128 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); 138 dbgs() << " " << TRI->getName(r)); 148 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); 159 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 172 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { 175 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 203 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { 212 dbgs() << " " << TRI->getName(Reg) << "=g" << 251 for (MCSubRegIterator SubRegs(Reg, TRI); SubReg [all...] |
H A D | RegisterPressure.cpp | 49 void RegisterPressure::increase(unsigned Reg, const TargetRegisterInfo *TRI, argument 54 TRI->getRegClassPressureSets(RC), 55 TRI->getRegClassWeight(RC).RegWeight); 59 TRI->getRegUnitPressureSets(Reg), 60 TRI->getRegUnitWeight(Reg)); 65 void RegisterPressure::decrease(unsigned Reg, const TargetRegisterInfo *TRI, argument 69 decreaseSetPressure(MaxSetPressure, TRI->getRegClassPressureSets(RC), 70 TRI->getRegClassWeight(RC).RegWeight); 73 decreaseSetPressure(MaxSetPressure, TRI->getRegUnitPressureSets(Reg), 74 TRI 79 dumpSetPressure(const std::vector<unsigned> &SetPressure, const TargetRegisterInfo *TRI) argument 315 const TargetRegisterInfo *TRI; member in class:RegisterOperands 533 computeExcessPressureDelta(ArrayRef<unsigned> OldPressureVec, ArrayRef<unsigned> NewPressureVec, RegPressureDelta &Delta, const TargetRegisterInfo *TRI) argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600ExpandSpecialInstrs.cpp | 60 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local 166 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local 174 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); 234 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); 235 Src0 = TRI.getSubReg(Src0, SubRegIndex); 236 Src1 = TRI.getSubReg(Src1, SubRegIndex); 239 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]); 240 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]); 241 Src1 = TRI [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AsmPrinter.cpp | 44 const TargetRegisterInfo *TRI, 50 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) { 62 const TargetRegisterInfo *TRI, 76 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) { 157 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local 170 if (printModifiedFPRAsmOperand(MO, TRI, AArch64::VPR128RegClass, O)) 202 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI, 207 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI, 225 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI, 229 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI, 43 printModifiedFPRAsmOperand(const MachineOperand &MO, const TargetRegisterInfo *TRI, const TargetRegisterClass &RegClass, raw_ostream &O) argument 61 printModifiedGPRAsmOperand(const MachineOperand &MO, const TargetRegisterInfo *TRI, const TargetRegisterClass &RegClass, raw_ostream &O) argument [all...] |
H A D | AArch64FrameLowering.h | 68 const TargetRegisterInfo *TRI) const; 72 const TargetRegisterInfo *TRI) const; 92 const TargetRegisterInfo *TRI,
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/external/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.h | 32 const ARMBaseRegisterInfo &TRI; member in class:llvm::ARMHazardRecognizer 45 TRI(tri), STI(sti), LastMI(0) {}
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H A D | Thumb1FrameLowering.h | 41 const TargetRegisterInfo *TRI) const; 45 const TargetRegisterInfo *TRI) const;
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H A D | Thumb1InstrInfo.h | 50 const TargetRegisterInfo *TRI) const; 56 const TargetRegisterInfo *TRI) const;
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H A D | Thumb2InstrInfo.h | 52 const TargetRegisterInfo *TRI) const; 58 const TargetRegisterInfo *TRI) const;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.h | 37 const TargetRegisterInfo *TRI) const; 47 const TargetRegisterInfo *TRI) const;
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H A D | HexagonFrameLowering.cpp | 214 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) { argument 215 MCSuperRegIterator SRI(Reg, TRI); 228 const TargetRegisterInfo *TRI) const { 249 unsigned SuperReg = uniqueSuperReg(Reg, TRI); 254 unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI); 255 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); 262 CSI[i+1].getFrameIdx(), SuperRegClass, TRI); 268 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 270 TRI); 282 const TargetRegisterInfo *TRI) cons [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.h | 45 const TargetRegisterInfo *TRI) const; 49 const TargetRegisterInfo *TRI) const;
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16FrameLowering.h | 37 const TargetRegisterInfo *TRI) const; 42 const TargetRegisterInfo *TRI) const;
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H A D | MipsFrameLowering.cpp | 104 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); local 113 for (const uint16_t *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) { 114 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize();
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.h | 36 const TargetRegisterInfo *TRI) const; 40 const TargetRegisterInfo *TRI) const;
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