Searched refs:r_dest (Results 1 - 16 of 16) sorted by relevance

/art/compiler/dex/quick/mips/
H A Dutility_mips.cc25 LIR* MipsMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { argument
28 DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble());
29 if (r_dest.IsDouble()) {
32 if (r_dest.IsSingle()) {
38 r_src = r_dest;
39 r_dest = t_opnd;
47 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_src.GetReg(), r_dest.GetReg());
48 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
76 * 1) r_dest is freshly returned from AllocTemp or
79 LIR* MipsMir2Lir::LoadConstantNoClobber(RegStorage r_dest, in argument
161 OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) argument
202 OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) argument
328 OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) argument
339 OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) argument
344 LoadConstantWide(RegStorage r_dest, int64_t value) argument
356 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument
455 LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size) argument
552 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument
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H A Dcodegen_mips.h35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
39 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
40 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
45 LIR* GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest);
141 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
147 void OpRegCopy(RegStorage r_dest, RegStorage r_src);
148 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
151 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
153 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorag
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H A Dint_mips.cc163 LIR* MipsMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { argument
165 if (r_dest.IsPair()) {
166 r_dest = r_dest.GetLow();
171 if (r_dest.IsFloat() || r_src.IsFloat())
172 return OpFpRegCopy(r_dest, r_src);
174 r_dest.GetReg(), r_src.GetReg());
175 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
181 void MipsMir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { argument
182 if (r_dest !
188 OpRegCopyWide(RegStorage r_dest, RegStorage r_src) argument
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H A Dtarget_mips.cc494 LIR* MipsMir2Lir::GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest) { argument
495 DCHECK(!r_dest.IsFloat()); // See RegClassForFieldLoadStore().
496 DCHECK(r_dest.IsPair());
504 OpRegCopyWide(r_dest, reg_ret);
/art/compiler/dex/quick/x86/
H A Dutility_x86.cc29 LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { argument
32 DCHECK(r_dest.IsFloat() || r_src.IsFloat());
33 DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble());
34 if (r_dest.IsDouble()) {
37 if (r_dest.IsSingle()) {
49 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg());
50 if (r_dest == r_src) {
78 * 1) r_dest is freshly returned from AllocTemp or
81 LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { argument
82 RegStorage r_dest_save = r_dest;
251 OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) argument
356 OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) argument
364 OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) argument
420 OpRegMem(OpKind op, RegStorage r_dest, RegLocation rl_value) argument
445 OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) argument
497 OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src, int value) argument
560 LoadConstantWide(RegStorage r_dest, int64_t value) argument
634 LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, RegStorage r_dest, OpSize size) argument
761 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument
766 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument
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H A Dcodegen_x86.h72 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
74 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
76 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
77 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
268 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
274 void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
275 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE;
278 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE;
280 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
281 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorag
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H A Dint_x86.cc123 LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { argument
125 if (r_dest.IsPair()) {
126 r_dest = r_dest.GetLow();
131 if (r_dest.IsFloat() || r_src.IsFloat())
132 return OpFpRegCopy(r_dest, r_src);
133 LIR* res = RawLIR(current_dalvik_offset_, r_dest.Is64Bit() ? kX86Mov64RR : kX86Mov32RR,
134 r_dest.GetReg(), r_src.GetReg());
135 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
141 void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorag argument
148 OpRegCopyWide(RegStorage r_dest, RegStorage r_src) argument
2020 OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset) argument
2033 OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset) argument
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H A Dfp_x86.cc63 RegStorage r_dest = rl_result.reg; local
66 if (r_dest == r_src2) {
68 OpRegCopy(r_src2, r_dest);
70 OpRegCopy(r_dest, r_src1);
71 NewLIR2(op, r_dest.GetReg(), r_src2.GetReg());
/art/compiler/dex/quick/arm64/
H A Dutility_arm64.cc110 LIR* Arm64Mir2Lir::LoadFPConstantValue(RegStorage r_dest, int32_t value) { argument
111 DCHECK(r_dest.IsSingle());
113 return NewLIR2(kA64Fmov2sw, r_dest.GetReg(), rwzr);
117 return NewLIR2(kA64Fmov2fI, r_dest.GetReg(), encoded_imm);
129 r_dest.GetReg(), 0, 0, 0, 0, data_target);
134 LIR* Arm64Mir2Lir::LoadFPConstantValueWide(RegStorage r_dest, int64_t value) { argument
135 DCHECK(r_dest.IsDouble());
137 return NewLIR2(kA64Fmov2Sx, r_dest.GetReg(), rxzr);
141 return NewLIR2(FWIDE(kA64Fmov2fI), r_dest.GetReg(), encoded_imm);
155 r_dest
392 LoadConstantNoClobber(RegStorage r_dest, int value) argument
456 LoadConstantWide(RegStorage r_dest, int64_t value) argument
680 OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) argument
690 OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) argument
695 OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, int shift) argument
763 OpRegRegRegExtend(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, A64RegExtEncodings ext, uint8_t amount) argument
801 OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) argument
805 OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) argument
809 OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value) argument
1024 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument
1107 LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale) argument
1197 LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size) argument
1274 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument
1289 LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, VolatileKind is_volatile) argument
1392 OpFpRegCopy(RegStorage r_dest, RegStorage r_src) argument
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H A Dcodegen_arm64.h75 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
77 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest,
79 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
81 LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale)
83 LIR* LoadConstantNoClobber(RegStorage r_dest, int value) OVERRIDE;
84 LIR* LoadConstantWide(RegStorage r_dest, int64_t value) OVERRIDE;
209 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
215 void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
216 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE;
219 LIR* OpMovRegMem(RegStorage r_dest, RegStorag
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H A Dint_arm64.cc301 LIR* Arm64Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { argument
302 bool dest_is_fp = r_dest.IsFloat();
309 DCHECK_EQ(r_dest.Is64Bit(), r_src.Is64Bit());
313 opcode = UNLIKELY(A64_REG_IS_SP(r_dest.GetReg())) ? kA64Add4RRdT : kA64Mov2rr;
320 if (r_dest.Is64Bit() && r_src.Is64Bit()) {
325 bool dest_is_double = r_dest.IsDouble();
337 if (r_dest.IsDouble()) {
347 r_dest = Check32BitReg(r_dest);
353 res = RawLIR(current_dalvik_offset_, opcode, r_dest
362 OpRegCopy(RegStorage r_dest, RegStorage r_src) argument
369 OpRegCopyWide(RegStorage r_dest, RegStorage r_src) argument
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/art/compiler/dex/quick/arm/
H A Dutility_arm.cc72 LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) { argument
73 DCHECK(RegStorage::IsSingle(r_dest));
78 NewLIR2(kThumb2Vmovs_IMM8, r_dest, 0);
80 return NewLIR3(kThumb2Vsubs, r_dest, r_dest, r_dest);
84 return NewLIR2(kThumb2Vmovs_IMM8, r_dest, encoded_imm);
93 r_dest, rs_r15pc.GetReg(), 0, 0, 0, data_target);
170 * 1) r_dest is freshly returned from AllocTemp or
173 LIR* ArmMir2Lir::LoadConstantNoClobber(RegStorage r_dest, in argument
375 OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) argument
385 OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) argument
390 OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, int shift) argument
459 OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) argument
463 OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) argument
641 LoadConstantWide(RegStorage r_dest, int64_t value) argument
692 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument
854 LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size) argument
965 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument
1143 OpFpRegCopy(RegStorage r_dest, RegStorage r_src) argument
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H A Dcodegen_arm.h35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
39 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
40 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
143 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
150 void OpRegCopy(RegStorage r_dest, RegStorage r_src);
151 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
154 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
156 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
157 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorag
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H A Dint_arm.cc401 LIR* ArmMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { argument
405 if (r_dest.IsPair()) {
406 r_dest = r_dest.GetLow();
411 if (r_dest.IsFloat() || r_src.IsFloat())
412 return OpFpRegCopy(r_dest, r_src);
413 if (r_dest.Low8() && r_src.Low8())
415 else if (!r_dest.Low8() && !r_src.Low8())
417 else if (r_dest.Low8())
421 res = RawLIR(current_dalvik_offset_, opcode, r_dest
428 OpRegCopy(RegStorage r_dest, RegStorage r_src) argument
435 OpRegCopyWide(RegStorage r_dest, RegStorage r_src) argument
615 GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops) argument
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/art/compiler/dex/quick/
H A Dgen_loadstore.cc30 LIR* Mir2Lir::LoadConstant(RegStorage r_dest, int value) { argument
31 if (IsTemp(r_dest)) {
32 Clobber(r_dest);
33 MarkInUse(r_dest);
35 return LoadConstantNoClobber(r_dest, value);
83 void Mir2Lir::LoadValueDirect(RegLocation rl_src, RegStorage r_dest) { argument
86 OpRegCopy(r_dest, rl_src.reg);
90 LoadConstantNoClobber(r_dest, mir_graph_->ConstantValue(rl_src));
96 LoadRefDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, kNotVolatile); local
98 Load32Disp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest); local
108 LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest) argument
119 LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest) argument
129 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, k64, kNotVolatile); local
138 LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest) argument
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H A Dmir_to_lir.h993 virtual LIR* LoadConstant(RegStorage r_dest, int value);
995 virtual LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { argument
996 return LoadBaseDisp(r_base, displacement, r_dest, kWord, kNotVolatile);
999 virtual LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { argument
1000 return LoadBaseDisp(r_base, displacement, r_dest, k32, kNotVolatile);
1003 virtual LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, argument
1005 return LoadBaseDisp(r_base, displacement, r_dest, kReference, is_volatile);
1008 virtual LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, argument
1010 return LoadBaseIndexed(r_base, r_index, r_dest, scale, kReference);
1019 virtual void LoadValueDirect(RegLocation rl_src, RegStorage r_dest);
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