| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 0d293e45b66c742fdbc3998209bb20ed6c5806bf |
|
22-Sep-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Provide basic type safety for array_pod_sort comparators.
This makes using array_pod_sort significantly safer. The implementation relies
on function pointer casting but that should be safe as we're dealing with void*
here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| d3d751804c1f9d0ac77bbc3a6be48ee3cee2043b |
|
31-Jul-2013 |
Andrew Trick <atrick@apple.com> |
comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| c408335bf5128cb24214cce95863d9717e4cdb76 |
|
31-Jul-2013 |
Andrew Trick <atrick@apple.com> |
Fix register pressure tables on ARM.
The heuristic that merges register pressure sets was bogus for ARM's S/D regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| bbf20d4d4af06f0410e7b3ffc71d9be751867067 |
|
31-Jul-2013 |
Andrew Trick <atrick@apple.com> |
Add tracing to the tblgen register pressure table generator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| bba663e30a61b138c8f76632f8cacf00d7b0649a |
|
25-Jul-2013 |
Andrew Trick <atrick@apple.com> |
RegPressure: Order the "pressure sets" by number of regunits per set.
This lets heuristics easily pick the most important set to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| a0ec3f9b7b826b9b40b80199923b664bad808cce |
|
14-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| b7110cf5b5e4832e8ded6db7ab7577e3cfa2c462 |
|
27-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
Improve the compression of the tablegen DiffLists by introducing a new sort
algorithm when assigning EnumValues to the synthesized registers.
The current algorithm, LessRecord, uses the StringRef compare_numeric
function. This function compares strings, while handling embedded numbers.
For example, the R600 backend registers are sorted as follows:
T1
T1_W
T1_X
T1_XYZW
T1_Y
T1_Z
T2
T2_W
T2_X
T2_XYZW
T2_Y
T2_Z
In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2
have an EnumValue offset of 6 from one another. However, in other parts
of the register bank, the scaling factors are different:
dEnum/dN = 5:
KC0_128_W
KC0_128_X
KC0_128_XYZW
KC0_128_Y
KC0_128_Z
KC0_129_W
KC0_129_X
KC0_129_XYZW
KC0_129_Y
KC0_129_Z
The diff lists do not work correctly because different kinds of registers have
different 'scaling factors'. This new algorithm, LessRecordRegister, tries to
enforce a scaling factor of 1. For example, the registers are now sorted as
follows:
T1
T2
T3
...
T0_W
T1_W
T2_W
...
T0_X
T1_X
T2_X
...
KC0_128_W
KC0_129_W
KC0_130_W
...
For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I
did see a few small regressions, but the differences were on the order of a
few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even
greater wins for targets with larger register files.
Patch reviewed by Jakob.
rdar://14006013
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 23ed37a6b76e79272194fb46597f7280661b828f |
|
01-Jun-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
Make SubRegIndex size mandatory, following r183020.
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| bed23081860275c79137f65d592920e7991b8198 |
|
31-May-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
Add a way to define the bit range covered by a SubRegIndex.
NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
the instances of SubRegIndex that have a comps template arg to use the
ComposedSubRegIndex class instead.
In TableGen land, this adds Size and Offset attributes to SubRegIndex,
and the ComposedSubRegIndex class, for which the Size and Offset are
computed by TableGen. This also adds an accessor in MCRegisterInfo, and
Size/Offsets for the X86 and ARM subreg indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 2275cfd75b65ede0f46f3cf914e76a38daf96417 |
|
28-May-2013 |
Chad Rosier <mcrosier@apple.com> |
Remove the MCRegAliasIterator tables and compute the aliases dynamically.
The size reduction in the RegDiffLists are rather dramatic. Here are a few
size differences for MCTargetDesc.o files (before and after) in bytes:
R600 - 36160B - 11184B - 69% reduction
ARM - 28480B - 8368B - 71% reduction
Mips - 816B - 576B - 29% reduction
One side effect of dynamically computing the aliases is that the iterator does
not guarantee that the entries are ordered or that duplicates have been removed.
The documentation implies this is a safe assumption and I found no clients that
requires these attributes (i.e., strict ordering and uniqueness).
My local LNT tester results showed no execution-time failures or significant
compile-time regressions (i.e., beyond what I would consider noise) for -O0g,
-O2 and -O3 runs on x86_64 and i386 configurations.
rdar://12906217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182783 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 997fa623fc14122153c58ddda8c90aa30f192cc8 |
|
16-May-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetRegisterInfo::getCoveringLanes().
This lane mask provides information about which register lanes
completely cover super-registers. See the block comment before
getCoveringLanes().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| f15fe8195b0a42d0e950f3694c4d6ccd4034804a |
|
26-Feb-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
[TableGen] Fix ICE on MSVC 2012 Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| f79c5e2f842e952d26a2aa380fa71d5917c865a0 |
|
31-Jan-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Clarify intent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| b50df4a3df6db2ace3c011267934d3d10bdcc8db |
|
10-Jan-2013 |
Jordan Rose <jordan_rose@apple.com> |
TableGen: Keep track of superclass reference ranges.
def foo : bar;
~~~
This allows us to produce more precise diagnostics about a certain
superclass, and even provide fixits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| eca1fcf3d2d8246c45648fea59bd21a4091f9115 |
|
05-Dec-2012 |
Andrew Trick <atrick@apple.com> |
RegisterPressure API. Add support for physical register units.
At build-time register pressure was always computed in terms of
register units. But the compile-time API was expressed in terms of
register classes because it was intended for virtual registers (and
physical register units weren't yet used anywhere in codegen).
Now that the codegen uses physreg units consistently, prepare for
tracking register pressure also in terms of live units, not live
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 4ffd89fa4d2788611187d1a534d2ed46adf1702c |
|
04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 61131ab15fd593a2e295d79fe2714e7bc21f2ec8 |
|
25-Oct-2012 |
Joerg Sonnenberger <joerg@bec.de> |
Remove exception handling usage from tblgen.
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 2c6d71388fb1b68ce6fdbb88642a95a24b27b2a7 |
|
25-Oct-2012 |
Joerg Sonnenberger <joerg@bec.de> |
Don't use stack unwinding to provide the location information for
SetTheory, but pass down the location explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 94c22716d60ff5edf6a98a3c67e0faa001be1142 |
|
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 7e2c793a2b5c746344652b6579e958ee42fafdcc |
|
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo 'iff' => 'if'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| d2c699706ceae4a118a8dcafbef73b85093e5390 |
|
12-Sep-2012 |
Owen Anderson <resistor@mac.com> |
Compute a map from register names to registers, rather than scanning the list of registers every time we want to look up a register by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| a6035773d8d29827a124e65c258adbf0dcbb1a5a |
|
11-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TRI::getSubRegIndexLaneMask().
Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.
The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.
Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| de0250728b1a9e69ca593168f1ea2ecef8e9bf95 |
|
11-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Clean the sub-reg index composition maps at emission.
Preserve the Composites map in the CodeGenSubRegIndex class so it can be
used to determine which sub-register indices can actually be composed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 376a8a773e38fdcd9102a40e08ab1e0661d645d9 |
|
23-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Print out the location of expanded multiclass defs in TableGen errors.
When reporting an error for a defm, we would previously only report the
location of the outer defm, which is not always where the error is.
Now we also print the location of the expanded multiclass defs:
lib/Target/X86/X86InstrSSE.td:2902:12: error: foo
defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
^
lib/Target/X86/X86InstrSSE.td:2801:11: note: instantiated from multiclass
defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
^
lib/Target/X86/X86InstrSSE.td:194:5: note: instantiated from multiclass
def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| d024a20bf78086e2bbe7f03ceecbe26c095d7a31 |
|
15-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a CoveringSubRegIndices field to SubRegIndex records.
This can be used to tell TableGen to use a specific SubRegIndex instead
of synthesizing one when discovering all sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| c97eda2c9e34f4c491f59bbac81af2fd63fef49d |
|
15-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make synthesized sub-register indexes available in the target namespace.
TableGen sometimes synthesizes missing sub-register indexes. Emit these
indexes as enumerators in the target namespace along with the
user-defined ones.
Also take this opportunity to stop creating new Record objects for
synthetic indexes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 2ca6b3c37498eebf1f729f85cee03aa38ea5bc65 |
|
27-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove support for 'CompositeIndices' and sub-register cycles.
Now that the weird X86 sub_ss and sub_sd sub-register indexes are gone,
there is no longer a need for the CompositeIndices construct in .td
files. Sub-register index composition can be specified on the
SubRegIndex itself using the ComposedOf field.
Also enforce unique names for sub-registers in TableGen. The same
sub-register cannot be available with multiple sub-register indexes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| d9b0b025612992a0b724eeca8bdf10b1d7a5c355 |
|
02-Jun-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix typos found by http://github.com/lyda/misspell-check
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| f52baf72c116d9cf8680d25a8e751ce354c7d44b |
|
30-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Emit register unit lists for each register.
Register units are already used internally in TableGen to compute
register pressure sets and overlapping registers. This patch makes them
available to the code generators.
The register unit lists are differentially encoded so they can be reused
for many related registers. This keeps the total size of the lists below
200 bytes for most targets. ARM has the largest table at 560 bytes.
Add an MCRegUnitIterator for traversing the register unit lists. It
provides an abstract interface so the representation can be changed in
the future without changing all clients.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| a9fdbbc55f640fecd3bb8df12fd205694c2f71a2 |
|
22-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Also compute TopoSigs in synthetic register classes.
CodeGenRegisterClass has two constructors. Both need to compute the
TopoSigs BitVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157271 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 3778aeb74864390bf763424c45cc355ac330fbc9 |
|
17-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use RegUnits to compute overlapping registers.
TableGen already computes register units as the basic unit of
interference. We can use that to compute the set of overlapping
registers.
This means that we can easily compute overlap sets for one register at a
time. There is no benefit to computing all registers at once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 40c6fb397d1e485aef8b4e1729ba9804784990c1 |
|
15-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Create a struct representing register units in TableGen.
Besides the weight, we also want to store up to two root registers per
unit. Most units will have a single root, the leaf register they
represent. Units created for ad hoc aliasing get two roots: The two
aliasing registers.
The root registers can be used to compute the set of overlapping
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| f402602199a3fc875bb9b6887869e647d0b49df2 |
|
14-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Consider ad hoc aliasing when building RegUnits.
Register units can be used to compute if two registers overlap:
A overlaps B iff units(A) intersects units(B).
With this change, the above holds true even on targets that use ad hoc
aliasing (currently only ARM). This means that register units can be
used to implement regsOverlap() more efficiently, and the register
allocator can use the concept to model interference.
When there is no ad hoc aliasing, the register units correspond to the
maximal cliques in the register overlap graph. This is optimal, no other
register unit assignment can have fewer units.
With ad hoc aliasing, weird things are possible, and we don't try too
hard to compute the maximal cliques. The current approach is always
correct, and it works very well (probably optimally) as long as the ad
hoc aliasing doesn't have cliques larger than pairs. It seems unlikely
that any target would need more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 31d938a6b1173c642f975d78417459d4d8cd3677 |
|
14-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Record the ad hoc aliasing graph in CodeGenRegister.
The ad hoc aliasing specified in the 'Aliases' list in .td files is
currently only used by computeOverlaps(). It will soon be needed to
build accurate register units as well, so build the undirected graph in
CodeGenRegister::buildObjectGraph() instead.
Aliasing is a symmetric relationship with only one direction specified
in the .td files. Make sure both directions are represented in
getExplicitAliases().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| b81cbc271faed9fa633920436cd7ae49750a9a42 |
|
14-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Compute topological signatures of registers.
TableGen creates new register classes and sub-register indices based on
the sub-register structure present in the register bank. So far, it has
been doing that on a per-register basis, but that is not very efficient.
This patch teaches TableGen to compute topological signatures for
registers, and use that to reduce the amount of redundant computation.
Registers get the same TopoSig if they have identical sub-register
structure.
TopoSigs are not currently exposed outside TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| ddd657d16d7716f29982e97c5fa3f3ff33770108 |
|
12-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Speed up computeComposites() by using the new SubReg -> SubIdx map.
TableGen doesn't need to search through the SubRegs map to find an
inverse entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156690 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 9df5ec3984c6197939e5a9b1d3b893e909ca0632 |
|
11-May-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove extraneous ; and the resulting warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 79e2045531cb4d1978be42591e9254c38a463d30 |
|
11-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Defer computation of SuperRegs.
Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| fcad79671f22c8994663c6780862b9c38d3609c3 |
|
11-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Compute secondary sub-registers.
The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:
Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3]
But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.
This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.
This will eventually enable the coalescer to handle copies of skewed
sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 148f392195dec8772ab4c5ac0d0c3b85fba0e5f8 |
|
10-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Precompute lists of explicit sub-registers and indices.
The .td files specify a tree of sub-registers. Store that tree as
ExplicitSubRegs lists in CodeGenRegister instead of extracting it from
the Record when needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 7b521ad6eea8ac25960a4efecb9578c18fbc0e93 |
|
10-May-2012 |
Andrew Trick <atrick@apple.com> |
Fix TableGen's RegPressureSet weight normalization to handle subreg DAGS.
I initially assumed that the subreg graph was a tree. That may not be true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 08dc5f2adb0da8d171e4b070f35cf66d7e12774b |
|
10-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix warning text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| ca313e1efa98910a7a5e7f4bf2ac1a70adb6e4fe |
|
10-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Compute a backwards SubReg -> SubRegIndex map for each register.
This mapping is for internal use by TableGen. It will not be exposed in
the generated files.
Unfortunately, the mapping is not completely well-defined. The X86 xmm
registers appear with multiple sub-register indices in the ymm
registers. This is because of the odd idempotent sub_sd and sub_ss
sub-register indices. I hope to be able to eliminate them entirely, so
we can require the sub-registers to form a tree.
For now, just place the canonical sub_xmm index in the mapping, and
ignore the idempotents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| da2be824346c316c6fc840de7b8493e3d587e785 |
|
10-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Rename getSubRegs() to computeSubRegs().
That's what it does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| a93090ccd914492550ee43befe1f0c2286b22fed |
|
05-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Order register classes by spill size first, members last.
This is still a topological ordering such that every register class gets
a smaller enum value than its sub-classes.
Placing the smaller spill sizes first makes a difference for the
super-register class bit masks. When looking for a super-register class,
we usually want the smallest possible kind of super-register. That is
now available as the first bit set in the bit mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 7855ec62c3b6b5b7e6d3fada589511abd964fdb3 |
|
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove TargetRegisterClass::SuperRegClasses.
This manually enumerated list of super-register classes has been
superceeded by the automatically computed super-register class masks
available through SuperRegClassIterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 3cbcffc4e5990209ce80a54e615f55245fe3b824 |
|
18-Apr-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
tblgen: remove duplicated newlines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155038 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| bfb4327baa5bbab78f0da4c8c069482878660a04 |
|
18-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Move a few more warnings to use PrintWarning().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| ec14cd7ddc66d47cd7927f18d8c11844c400367e |
|
11-Apr-2012 |
Andrew Trick <atrick@apple.com> |
TableGen's regpressure: emit per-registerclass weight limits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 5c1761d486deb47648fa1b854692f4b64a35f0e2 |
|
11-Apr-2012 |
Andrew Trick <atrick@apple.com> |
TableGen'd regpressure: register unit set pruning.
The pruning is more complete if it is not done incrementally. The code
is also a tad less convluted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| aa744e2c44b530fc2f7b266fb61f22976cb4ea0f |
|
11-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Table-generated register pressure fixes.
Handle mixing allocatable and unallocatable register gracefully.
Simplify the pruning of register unit sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 4b745588c935a99cd3fcc574bc6e4934c2e85397 |
|
11-Apr-2012 |
Andrew Trick <atrick@apple.com> |
TableGen/reginfo potential bug: typo from previous checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 0fb0678106c490b38343487ab121461f635875a0 |
|
10-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Fix for register pressure tables.
Recent refactoring introduced a bug. Fix: added buildRegUnitSets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| c72e08b4a95e494d3bfdf1262ea8b28f614ac40e |
|
10-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Use std::includes instead of my own implementation.
Jakob's review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 176194d4ee2774bc135ababc5bd6c6c9f606b2a5 |
|
10-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Added register unit sets to the target description.
This is a new algorithm that finds sets of register units that can be
used to model registers pressure. This handles arbitrary, overlapping
register classes. Each register class is associated with a (small)
list of pressure sets. These are the dimensions of pressure affected
by the register class's liveness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| d35ac3c8bc37ab383b10a04b9c8b1087d6b2bc45 |
|
10-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Added register unit weights to the target description.
This is a new algorithm that associates registers with weighted
register units to accuretely model their effect on register
pressure. This handles registers with multiple overlapping
subregisters. It is possible, but almost inconceivable that the
algorithm fails to find an exact solution for a target description. If
an exact solution cannot be found, an inexact, but reasonable solution
will be chosen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 5aeda3f07684e555f19813e41b7fc101434cfe64 |
|
03-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Cleanup set_union usage. The same thing but a bit cleaner now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| f1275959b2b6ac5212e8b5547251b0303168b0b1 |
|
03-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Use std::set_union instead of nasty custom code.
I just noticed Jakob's examples of the proper application of
std::set... routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 9f2a9d741f58f0a2a591ec16e5e038c905142dbc |
|
31-Mar-2012 |
Andrew Trick <atrick@apple.com> |
comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153796 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| dd9a50196cd75dbcb2bd604754cd62f8c1f30357 |
|
31-Mar-2012 |
Andrew Trick <atrick@apple.com> |
Introduce Register Units: Give each leaf register a number.
First small step toward modeling multi-register multi-pressure. In the
future, register units can also be used to model liveness and
aliasing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| c6a96ff6aeeb77e1007364e5603b72f3ab4cc7bd |
|
29-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add more constness to CodeGenRegisters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| b5af2d943ed568f2f4cac545b6dfb150ae9d73aa |
|
02-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Specify SubRegIndex components on the index itself.
It is simpler to define a composite index directly:
def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;
Than specifying the composite indices on each register:
CompositeIndices = [(ssub_2 dsub_1, ssub_0),
(ssub_3 dsub_1, ssub_1)] in ...
This also makes it clear that SubRegIndex composition is supposed to be
unique.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| ee599209e613cbe11ca67e8d084d2fc37d679f61 |
|
01-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix a bug in the TopoOrderRC comparison function.
The final tie breaker comparison also needs to return +/-1, or 0.
This is not a less() function.
This could cause otherwise identical super-classes to be ordered
unstably, depending on what the system qsort routine does with a bad
compare function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 90498b195ba759cf4f2a98da4e46fb9a2b580396 |
|
31-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move the composite map into CodeGenSubRegIndex.
Each SubRegIndex keeps track of how it composes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 5fcc156344e0d38fa5f5eab3d9193b859b27b45e |
|
31-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a TableGen CodeGenSubRegIndex class.
This class is used to represent SubRegIndex instances instead of the raw
Record pointers that were used before.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 31867660cb81ea2b1d1a6ffa7d09c91acb754a8b |
|
18-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a CoveredBySubRegs property to Register descriptions.
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.
Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers. For example, the
ARM registers D8-D15 are callee-saved. This now automatically implies
that Q4-Q7 are call-preserved.
Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| ec572539dd5660f9ca42027ac04df3a3f8c0cab1 |
|
17-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TableGen support for callee saved registers.
Targets can now add CalleeSavedRegs defs to their *CallingConv.td file.
TableGen will use this to create a *_SaveList array suitable for
returning from getCalleeSavedRegs() as well as a *_RegMask bit mask
suitable for returning from getCallPreservedMask().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 794481d5ca75c1e614625f8a9487b8fa9db9d4d8 |
|
13-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Skip the NAME field when forming tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148147 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 8dd6f0c8353f80de6526810899f271d539f6929c |
|
13-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Delete CodeInit and CodeRecTy from TableGen.
The code type was always identical to a string anyway. Now it is simply
a synonym. The code literal syntax [{...}] is still valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 570f9a972e02830d1ca223743dd6b4cc4fdf9549 |
|
19-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Emit a getMatchingSuperRegClass() implementation for every target.
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| a9f65b9a1f57dcf546399ac32bf89d71d20df5b9 |
|
19-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Synthesize register classes for TRI::getMatchingSuperRegClass().
Teach TableGen to create the missing register classes needed for
getMatchingSuperRegClass() to return maximal results. The function is
still not auto-generated, so it still returns inexact results.
This produces these new register classes:
ARM:
QQPR_with_dsub_0_in_DPR_8
QQQQPR_with_dsub_0_in_DPR_8
X86:
GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP
GR64_with_sub_16bit_in_GR16_NOREX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP
GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_with_sub_32bit_in_GR32_TC
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC
GR64_with_sub_32bit_in_GR32_AD
GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX
The other targets in the tree are not weird enough to be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| fec33444c5ca22e0338fdac0fcaee2644bd756af |
|
16-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Extract a method. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| d4c826f64866295fcbfa472d812bd3ec3a5e4c9f |
|
15-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use the proper comparator for set_intersection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 7e56831a6804812b2295c5446a05f4ec457b6b3e |
|
15-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Synthesize missing register class intersections.
The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B. This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.
In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).
This introduces these synthetic register classes:
ARM:
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
tGPR_and_tcGPR
hGPR_and_tcGPR
X86:
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR64_NOSP_and_GR64_TC
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_TC
GR32_NOAX_and_GR32_NOSP
GR64_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_ABCD_and_GR32_NOAX
GR64_ABCD_and_GR64_TC
GR32_NOAX_and_GR32_TC
GR32_AD_and_GR32_NOAX
Other targets are unaffected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 1b3d218880a7147caeb58f2604af1df26a409f7d |
|
12-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Extract a method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 845d2c0c776abce551d16f7b1b7dc1f4d4df1a27 |
|
05-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TRI::getSubClassWithSubReg(RC, Idx) function.
This function is used to constrain a register class to a sub-class that
supports the given sub-register index.
For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.
The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.
The version provided by TableGen is usually adequate, but targets can
override.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| dae7909be3158c44c9bc3d7d33782430b88bea77 |
|
04-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Properly use const_iterator.
This should unbreak the Windows build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| babf0569e2e4f204f9a304416cc4acc349d8f836 |
|
04-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach TableGen to infer missing register classes.
The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.
This patch implements the easiest form of register class inference: For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.
This does create some new register classes for the targets in the tree:
ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td
file on purpose because it only has two registers. InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.
PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8. I think that might be an omission?
X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:
GR64_with_sub_8bit
GR64_TC_with_sub_8bit
GR64_NOREX_with_sub_8bit
GR64_TC_with_sub_8bit_hi
The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| cc0c975b7db95ce6bc865c56a3016bf0d4f83304 |
|
04-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
TableGen: Store all allocation orders together.
There is no need to keep the primary order separate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 6fea31e7300fe012b0b2984d6bc0338d02b054d3 |
|
04-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
TableGen: Privatize CodeGenRegisterClass::TheDef and Name.
When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference. All register classes must have a
name, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 877b6d43d4183e7b4bb6c99038c0d2b184dd3b3c |
|
04-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
TableGen: Don't add synthetic Records to the RecordKeeper.
The RecordKeeper could be shared by multiple target instances, causing
duplicate record errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 7c788888872233748da10a8177a9a1eb176c1bc8 |
|
01-Oct-2011 |
Peter Collingbourne <peter@pcc.me.uk> |
Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 52e7dfadc65257f05480de6e70da00373a8954d1 |
|
01-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().
All the sub-class bit vectors are computed when first creating the
register bank.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| f9a4bb78dadc12c7c1e604c6f17b63a71305c2ca |
|
01-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Compute lists of super-classes in CodeGenRegisterClass.
Use these lists instead of computing them on the fly in
RegisterInfoEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 203e0b17dd6049d64cb4ed7c4da09747204e6463 |
|
30-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Precompute a bit vector of register sub-classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 7dcaa5b0fb56468e774044d3b887c21b2d484a1c |
|
30-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Order register classes topologically.
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.
This will be used to simplify some sub-class operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 29f018cee616e4082e5005bc9adee4dc777e621c |
|
30-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch to ArrayRef<CodeGenRegisterClass*>.
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 05bce0beee87512e52428d4b80f5a8e79a949576 |
|
30-Jul-2011 |
David Greene <greened@obbligato.org> |
Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| dcd35c797d458d8b1dbc36cf7f1504166d5b2f16 |
|
29-Jul-2011 |
David Greene <greened@obbligato.org> |
[AVX] Create Inits Via Factory Method
Replace uses of new *Init with *Init::get. This hides the allocation
implementation so that we can unique Inits in various ways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136486 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| f37dd02f7743ebd2424480361f5a7db510495c4f |
|
29-Jul-2011 |
David Greene <greened@obbligato.org> |
[AVX] Constify Inits
Make references to Inits const everywhere. This is the final step
before making them unique.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 77f8274c7d4bfb5e2a449eb49dc78dcae37e5457 |
|
18-Jul-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Intern all RecTy subclass instances to avoid duplicates.
Make all of the RecTy constructors private, and use get() factory
methods instead. Return singleton instances when it makes sense.
ListTy instance pointers are stored in the element RecTy instance.
BitsRecTy instance pointers, one per length, are stored in a static vector.
Also unique DefInit instances. A Record has a unique DefInit which
has a unique RecordRecTy instance.
This saves some 200k-300k RecTy allocations when parsing ARM.td. It
reduces TableGen's heap usage by almost 50%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| d568b3f55294917d1cc701da14a8a7daeb6563e6 |
|
12-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 5e3cb47beada349cdde5cb023127491f46b88a7f |
|
11-Jul-2011 |
David Greene <greened@obbligato.org> |
Use get(0 Instead of Create()
Respond to some feedback asking for a name change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| d4a9066c93da9a5aab47ca228d82e796fdec70c0 |
|
11-Jul-2011 |
David Greene <greened@obbligato.org> |
[AVX] Make Inits Foldable
Manage Inits in a FoldingSet. This provides several benefits:
- Memory for Inits is properly managed
- Duplicate Inits are folded into Flyweights, saving memory
- It enforces const-correctness, protecting against certain classes
of bugs
The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen. This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 0b6a44afb92fed0365b6709c1f46b0c5e49e1a72 |
|
22-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Consolidate some TableGen diagnostic helper functions.
TableGen had diagnostic printers sprinkled about in a few places. Pull them
together into a single location in Error.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133568 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 9b718e88642963bfb519c47b70d1daf5d2126325 |
|
20-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Skip fields that don't exist in the Register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 4ce25d5d69704a7a4aa4bcecbe4c7345b50b771a |
|
20-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a RegisterTuples class to Target.td and TableGen.
A RegisterTuples instance is used to synthesize super-registers by
zipping together lists of sub-registers. This is useful for generating
pseudo-registers representing register sequence constraints like 'two
consecutive GPRs', or 'an even-odd pair of floating point registers'.
The RegisterTuples def can be used in register set operations when
building register classes. That is the only way of accessing the
synthesized super-registers.
For example, the ARM QQ register class of pseudo-registers could have
been formed like this:
// Form pairs Q0_Q1, Q2_Q3, ...
def QQPairs : RegisterTuples<[qsub_0, qsub_1],
[(decimate QPR, 2),
(decimate (shl QPR, 1), 2)]>;
def QQ : RegisterClass<..., (add QQPairs)>;
Similarly, pseudo-registers representing '3 consecutive D-regs with
wraparound' look like:
// Form D0_D1_D2, D1_D2_D3, ..., D30_D31_D0, D31_D0_D1.
def DSeqTriples : RegisterTuples<[dsub_0, dsub_1, dsub_2],
[(rotl DPR, 0),
(rotl DPR, 1),
(rotl DPR, 2)]>;
TableGen automatically computes aliasing information for the synthesized
registers.
Register tuples are still somewhat experimental. We still need to see
how they interact with MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133407 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| c6596e2edc406298ff65d27633bd898613533c0b |
|
18-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use the correct comparator to avoid depending on pointer values.
This should fix the Linux buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| abdbc84b4ed4276ed3def50f554e3ba156325717 |
|
18-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Store CodeGenRegisters as pointers so they won't be reallocated.
Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 54c47c1ce94b9e549ef768e80fd004788d13ce85 |
|
18-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove MethodProtos/MethodBodies and allocation_order_begin/end.
Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.
The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.
It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| b4c704877d1600852a55ab7bef2918a7c0af5e0d |
|
18-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Provide AltOrders for specifying alternative allocation orders.
A register class can define AltOrders and AltOrderSelect instead of
defining method protos and bodies. The AltOrders lists can be defined
with set operations, and TableGen can verify that the alternative
allocation orders only contain valid registers.
This is currently an opt-in feature, and it is still possible to
override allocation_order_begin/end. That will not be true for long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 59f26aadce1bb985b9befe841fc106c891e1c728 |
|
15-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use a SetTheory instance to expand register lists in register classes.
This prepares tablegen to compute register lists from set theoretic dag
expressions. This doesn't really make any difference as long as
Target.td still declares RegisterClass::MemberList as [Register].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| ae1920b1efa72c1789d562df4746110d0c2e10bd |
|
15-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Give CodeGenRegisterClass a real sorted member set.
Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.
Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 7b9cafde5e3faec22bbfbbc90cca0876968abad9 |
|
15-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move the list of register classes into CodeGenRegBank as well.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| 026dc223aeef2579d63f395007491e37d6cde3a0 |
|
12-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Compute lists of sub-regs, super-regs, and overlapping regs.
Besides moving structural computations to CodeGenRegisters.cpp, this
also well-defines the order of these lists:
- Sub-register lists come from a pre-order traversal of the graph
defined by the SubRegs lists in the .td files.
- Super-register lists are topologically ordered so no register comes
before any of its sub-registers. When the sub-register graph is not a
tree, independent super-registers appear in numerical order.
- Lists of overlapping registers are ordered according to register
number.
This reverses the order of the super-regs lists, but nobody was
depending on that. The previous order of the overlaps lists was odd, and
it may have depended on the precise behavior of std::stable_sort.
The old computations are still there, but will be removed shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| b5923db192d2aa938ff3c12aaac87d80ab649625 |
|
11-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move the list of registers into CodeGenRegBank.
Also move the sub-register index computations from RegisterInfoEmitter
into CodeGenRegBank.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| dc29c447136aabf05f48a7119e48065c3b4cee9b |
|
10-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move some sub-register index calculations to CodeGenRegisters.cpp
Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|
| f1e2b23dfabb74249c2f1828dc902bd4bda52aa8 |
|
09-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move TableGen's register bank classes to their own source file.
I'll be moving some more code there to gather all of the
register-specific stuff in one place. Currently it is shared between
CodeGenTarget and RegisterInfoEmitter.
The plan is that CodeGenRegisters can compute the full register bank
structure while RegisterInfoEmitter only will handle the printing part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.cpp
|