| /external/llvm/lib/CodeGen/ |
| H A D | UnreachableBlockElim.cpp | 124 MachineDominatorTree *MDT = getAnalysisIfAvailable<MachineDominatorTree>(); local
145 if (MDT && MDT->getNode(BB)) MDT->eraseNode(BB);
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| H A D | DFAPacketizer.cpp | 109 MachineDominatorTree &MDT, bool IsPostRA);
116 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
118 ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) {
129 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
133 VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
115 DefaultVLIWScheduler( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, bool IsPostRA) argument
128 VLIWPacketizerList( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, bool IsPostRA) argument
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| H A D | LiveRangeCalc.cpp | 24 MachineDominatorTree *MDT,
29 DomTree = MDT;
22 reset(const MachineFunction *mf, SlotIndexes *SI, MachineDominatorTree *MDT, VNInfo::Allocator *VNIA) argument
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| H A D | SplitKit.h | 216 MachineDominatorTree &MDT; member in class:llvm::SplitEditor
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| H A D | PostRASchedulerList.cpp | 135 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
191 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
195 : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) {
254 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); local
287 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
190 SchedulePostRATDList( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs) argument
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| H A D | InlineSpiller.cpp | 64 MachineDominatorTree &MDT; member in class:__anon25751::InlineSpiller
149 MDT(pass.getAnalysis<MachineDominatorTree>()),
460 MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) {
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| H A D | LiveDebugVariables.cpp | 230 /// @param MDT Dominator tree.
234 LiveIntervals &LIS, MachineDominatorTree &MDT,
253 LiveIntervals &LIS, MachineDominatorTree &MDT,
289 MachineDominatorTree *MDT; member in class:__anon25756::LDVImpl
504 LiveIntervals &LIS, MachineDominatorTree &MDT,
553 MDT.getNode(MBB)->getChildren();
637 MachineDominatorTree &MDT,
653 extendDef(Idx, LocNo, nullptr, nullptr, nullptr, LIS, MDT, UVS);
666 extendDef(Idx, LocNo, LI, VNI, &Kills, LIS, MDT, UVS);
677 extendDef(Idx, LocNo, LR, VNI, nullptr, LIS, MDT, UV
501 extendDef(SlotIndex Idx, unsigned LocNo, LiveRange *LR, const VNInfo *VNI, SmallVectorImpl<SlotIndex> *Kills, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument
634 computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAGInstrs.h | 79 const MachineDominatorTree &MDT; member in class:llvm::ScheduleDAGInstrs
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| H A D | MachineScheduler.h | 105 const MachineDominatorTree *MDT; member in struct:llvm::MachineSchedContext
253 : ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, IsPostRA,
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCCTRLoops.cpp | 139 MachineDominatorTree *MDT; member in struct:__anon26082::PPCCTRLoopsVerify
640 MDT = &getAnalysis<MachineDominatorTree>();
647 if (!MDT->isReachableFromEntry(MBB))
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| /external/llvm/lib/Target/R600/ |
| H A D | R600Packetizer.cpp | 152 MachineDominatorTree &MDT)
153 : VLIWPacketizerList(MF, MLI, MDT, true),
333 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); local
336 R600PacketizerList Packetizer(Fn, MLI, MDT);
151 R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT) argument
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| H A D | AMDILCFGStructurizer.cpp | 170 MDT = &getAnalysis<MachineDominatorTree>();
171 DEBUG(MDT->print(dbgs(), (const llvm::Module*)nullptr););
181 MachineDominatorTree *MDT; member in class:__anon26106::AMDGPUCFGStructurizer
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64CollectLOH.cpp | 619 const MachineDominatorTree *MDT) {
628 if (!MDT->dominates(L2, L1)) {
703 const MachineDominatorTree *MDT) {
715 if (!MDT->dominates(Def, Instr))
732 return MDT->dominates(Def, Instr);
786 const MachineDominatorTree *MDT) {
810 if (!isCandidate(Use.first, UseToDefs, MDT)) {
1047 const MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>(); local
1087 computeADRP(ADRPToReachingDefs, *AArch64FI, MDT);
1104 MDT);
617 computeADRP(const InstrToInstrs &UseToDefs, AArch64FunctionInfo &AArch64FI, const MachineDominatorTree *MDT) argument
701 isCandidate(const MachineInstr *Instr, const InstrToInstrs &UseToDefs, const MachineDominatorTree *MDT) argument
783 computeOthers(const InstrToInstrs &UseToDefs, const InstrToInstrs *DefsPerColorToUses, AArch64FunctionInfo &AArch64FI, const MapRegToId &RegToId, const MachineDominatorTree *MDT) argument
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVLIWPacketizer.cpp | 121 MachineDominatorTree &MDT,
187 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT,
189 : VLIWPacketizerList(MF, MLI, MDT, true){
196 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); local
200 HexagonPacketizerList Packetizer(Fn, MLI, MDT, MBPI);
186 HexagonPacketizerList( MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT, const MachineBranchProbabilityInfo *MBPI) argument
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| H A D | HexagonHardwareLoops.cpp | 66 MachineDominatorTree *MDT; member in struct:__anon26012::HexagonHardwareLoops
303 MDT = &getAnalysis<MachineDominatorTree>();
594 if (!MDT->properlyDominates(DefBB, Header))
601 if (!MDT->properlyDominates(DefBB, Header))
1049 if (!MDT->dominates(BBDef, Preheader))
1055 if (!MDT->properlyDominates(BBDef, L->getHeader()))
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