/external/smack/src/org/xbill/DNS/ |
H A D | Flags.java | 29 public static final byte RA = 8; field in class:Flags 49 flags.add(RA, "ra");
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/external/clang/test/CodeGenCXX/ |
H A D | devirtualize-virtual-function-calls-final.cpp | 164 struct RA { struct in namespace:Test9 169 struct RC final : public RA { 185 return static_cast<RA*>(x)->f();
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/external/llvm/lib/MC/ |
H A D | MCSubtargetInfo.cpp | 46 const MCReadAdvanceEntry *RA, 56 ReadAdvanceTable = RA; 40 InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
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/external/clang/test/Layout/ |
H A D | ms-x86-pack-and-align.cpp | 430 struct RA {}; struct 441 struct __declspec(align(8)) RB2 : virtual RA { 445 struct __declspec(align(8)) RB3 : virtual RA { 476 // CHECK-NEXT: 1028 | struct RA (virtual base) (empty) 484 // CHECK-NEXT: 2052 | struct RA (virtual base) (empty) 519 // CHECK-X64-NEXT: 1028 | struct RA (virtual base) (empty) 527 // CHECK-X64-NEXT: 2052 | struct RA (virtual base) (empty)
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H A D | ms-x86-alias-avoidance-padding.cpp | 301 struct RA {}; struct 306 struct RX0 : RB, RA {}; 307 struct RX1 : RA, RB {}; 308 struct RX2 : RA { char a; }; 309 struct RX3 : RA { RB a; }; 310 struct RX4 { RA a; char b; }; 311 struct RX5 { RA a; RB b; }; 313 struct RX7 : virtual RW { RA a; }; 314 struct RX8 : RA, virtual RW {}; 326 // CHECK-NEXT: 1 | struct RA (bas [all...] |
/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.cpp | 55 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; local 58 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCTargetDesc.cpp | 247 unsigned RA = (TheTriple.getArch() == Triple::x86_64) local 252 InitX86MCRegisterInfo(X, RA, 255 RA);
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/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineSimplifyDemanded.cpp | 722 APInt RA = Rem->getValue().abs(); local 723 if (RA.isPowerOf2()) { 724 if (DemandedMask.ult(RA)) // srem won't affect demanded bits 727 APInt LowBits = RA - 1;
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/external/chromium_org/third_party/skia/third_party/lua/src/ |
H A D | lvm.c | 489 #define RA(i) (base+GETARG_A(i)) macro 553 ra = RA(i); 659 ra = RA(i); /* 'luav_concat' may invoke TMs and move the stack */ 800 ra = RA(i); 849 ra = RA(i); /* previous call may change the stack */
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 438 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA); 600 unsigned RA = STI.isGP64bit() ? Mips::RA_64 : Mips::RA; local 612 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
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H A D | MipsISelLowering.cpp | 1888 unsigned RA = Subtarget->isABI_N64() ? Mips::RA_64 : Mips::RA; local 1891 // Return RA, which contains the return address. Mark it an implicit live-in. 1892 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
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/external/llvm/lib/Transforms/IPO/ |
H A D | DeadArgumentElimination.cpp | 153 void MarkValue(const RetOrArg &RA, Liveness L, 155 void MarkLive(const RetOrArg &RA); 157 void PropagateLiveness(const RetOrArg &RA); 619 /// MarkValue - This function marks the liveness of RA depending on L. If L is 621 /// such that RA will be marked live if any use in MaybeLiveUses gets marked 623 void DAE::MarkValue(const RetOrArg &RA, Liveness L, argument 626 case Live: MarkLive(RA); break; 633 Uses.insert(std::make_pair(*UI, RA)); 658 void DAE::MarkLive(const RetOrArg &RA) { argument 659 if (LiveFunctions.count(RA 671 PropagateLiveness(const RetOrArg &RA) argument [all...] |
H A D | MergeFunctions.cpp | 450 Attribute RA = *RI; local 451 if (LA < RA) 453 if (RA < LA) 553 const ConstantArray *RA = cast<ConstantArray>(R); local 560 cast<Constant>(RA->getOperand(i))))
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/external/libpcap/ |
H A D | tokdefs.h | 90 RA = 308, enumerator in enum:yytokentype 211 #define RA 308 macro
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H A D | grammar.c | 397 RA = 308, enumerator in enum:yytokentype 518 #define RA 308 macro 1034 "ADDR4", "RA", "TA", "LINK", "GEQ", "LEQ", "NEQ", "ID", "EID", "HID",
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/external/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 239 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, argument 252 RAReg = RA;
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/external/llvm/lib/Analysis/ |
H A D | ValueTracking.cpp | 536 APInt RA = Rem->getValue().abs(); local 537 if (RA.isPowerOf2()) { 538 APInt LowBits = RA - 1; 573 APInt RA = Rem->getValue(); local 574 if (RA.isPowerOf2()) { 575 APInt LowBits = (RA - 1);
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H A D | ScalarEvolution.cpp | 507 const Argument *RA = cast<Argument>(RV); local 508 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo(); 542 const APInt &RA = RC->getValue()->getValue(); local 543 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth(); 546 return LA.ult(RA) ? -1 : 1; 551 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS); local 554 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop(); 563 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands(); 569 long X = compare(LA->getOperand(i), RA->getOperand(i)); 3991 const SCEV *RA [all...] |
/external/deqp/framework/common/ |
H A D | tcuTexture.hpp | 50 RA, enumerator in enum:tcu::TextureFormat::ChannelOrder
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H A D | tcuTexture.cpp | 137 static const Channel RA[] = { CHANNEL_0, CHANNEL_ZERO, CHANNEL_ZERO, CHANNEL_1 }; local 154 case TextureFormat::RA: return RA; 178 static const int RA[] = { 0, 3 }; local 195 case TextureFormat::RA: return RA; 245 case TextureFormat::RA: return 2; 487 case RA: numChannels = 2; break; 3595 case TextureFormat::RA: return str << "RA"; [all...] |
/external/pcre/dist/sljit/ |
H A D | sljitNativeTILEGX_64.c | 77 #define RA 55 macro 1212 FAIL_IF(ST_ADD(ADDR_TMP_mapped, RA, -8)); 1283 FAIL_IF(LD(RA, ADDR_TMP_mapped)); 1333 return JR(RA); 1612 return ADD(reg_map[dst], RA, ZERO); 1615 return emit_op_mem(compiler, WORD_DATA, RA, dst, dstw); 1625 FAIL_IF(ADD(RA, reg_map[src], ZERO)); 1628 FAIL_IF(emit_op_mem(compiler, WORD_DATA | LOAD_DATA, RA, src, srcw)); 1631 FAIL_IF(load_immediate(compiler, RA, srcw)); 1633 return JR(RA); [all...] |
/external/clang/lib/CodeGen/ |
H A D | ItaniumCXXABI.cpp | 214 const ReturnAdjustment &RA) override; 1423 const ReturnAdjustment &RA) { 1424 return performTypeAdjustment(CGF, Ret, RA.NonVirtual, 1425 RA.Virtual.Itanium.VBaseOffsetOffset, 1422 performReturnAdjustment(CodeGenFunction &CGF, llvm::Value *Ret, const ReturnAdjustment &RA) argument
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H A D | MicrosoftCXXABI.cpp | 254 const ReturnAdjustment &RA) override; 1631 const ReturnAdjustment &RA) { 1632 if (RA.isEmpty()) 1637 if (RA.Virtual.Microsoft.VBIndex) { 1638 assert(RA.Virtual.Microsoft.VBIndex > 0); 1643 GetVBaseOffsetFromVBPtr(CGF, V, RA.Virtual.Microsoft.VBPtrOffset, 1644 IntSize * RA.Virtual.Microsoft.VBIndex, &VBPtr); 1648 if (RA.NonVirtual) 1649 V = CGF.Builder.CreateConstInBoundsGEP1_32(V, RA.NonVirtual); 1630 performReturnAdjustment(CodeGenFunction &CGF, llvm::Value *Ret, const ReturnAdjustment &RA) argument
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/external/llvm/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 538 const APInt &RA = RC->getValue()->getValue(); local 541 if (RA.isAllOnesValue()) 544 if (RA == 1) 553 const APInt &RA = RC->getValue()->getValue(); local 554 if (LA.srem(RA) != 0) 556 return SE.getConstant(LA.sdiv(RA));
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 2283 const APInt &RA = Rem->getAPIntValue().abs(); local 2284 if (RA.isPowerOf2()) { 2285 APInt LowBits = RA - 1; 2307 const APInt &RA = Rem->getAPIntValue(); local 2308 if (RA.isPowerOf2()) { 2309 APInt LowBits = (RA - 1);
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