Searched defs:RegNum (Results 1 - 13 of 13) sorted by relevance

/external/llvm/lib/Target/ARM/
H A DARMCodeEmitter.cpp1293 unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg()); local
1295 RegNum < 16);
1296 Binary |= 0x1 << RegNum;
H A DARMLoadStoreOptimizer.cpp747 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); local
753 ((isNotVFP && RegNum > PRegNum) ||
754 ((Count < Limit) && RegNum == PRegNum+1)) &&
759 PRegNum = RegNum;
/external/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp267 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); local
269 FPUBitmask |= (3 << RegNum);
275 FPUBitmask |= (1 << RegNum);
282 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); local
283 CPUBitmask |= (1 << RegNum);
/external/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp158 unsigned RegNum; member in struct:__anon26131::SparcOperand::RegOp
205 return Reg.RegNum;
299 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, argument
302 Op->Reg.RegNum = RegNum;
324 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
347 Op.Reg.RegNum = Reg;
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp1545 unsigned RegNum = GetX86RegNum(MO) << 4; local
1547 RegNum |= 1 << 7;
1555 RegNum |= Val;
1558 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
/external/clang/include/clang/Basic/
H A DTargetInfo.h596 const unsigned RegNum; member in struct:clang::TargetInfo::AddlRegName
/external/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp668 unsigned RegNum = RegMap[Reg]; local
690 Ret |= (RegNum & 0x0FFFFFFF);
/external/llvm/lib/Target/R600/
H A DAMDILCFGStructurizer.cpp236 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
238 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
515 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
521 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false);
526 int NewOpcode, int RegNum) {
531 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false);
514 insertCondBranchBefore(MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode, int RegNum, DebugLoc DL) argument
525 insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum) argument
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1279 unsigned RegNum = Registers[i]->EnumValue; local
1280 if (AllocatableRegs.count(RegNum))
1283 UberSetIDs.join(0, RegNum);
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp173 unsigned RegNum; member in struct:__anon25952::AArch64Operand::RegOp
178 unsigned RegNum; member in struct:__anon25952::AArch64Operand::VectorListOp
353 return Reg.RegNum;
358 return VectorList.RegNum;
885 Reg.RegNum);
889 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
894 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].contains(Reg.RegNum);
1588 CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) { argument
1590 Op->Reg.RegNum = RegNum;
1598 CreateVectorList(unsigned RegNum, unsigned Count, unsigned NumElements, char ElementKind, SMLoc S, SMLoc E, MCContext &Ctx) argument
1876 unsigned RegNum = isVector ? matchVectorRegName(Name) local
1901 unsigned RegNum = matchRegisterNameAlias(lowerCase, false); local
1931 unsigned RegNum = matchRegisterNameAlias(Head, true); local
2930 unsigned RegNum = matchRegisterNameAlias(Tok.getString().lower(), false); local
4050 unsigned RegNum = tryParseRegister(); local
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/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp177 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
1592 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { argument
1593 if (RegNum >
1597 return getReg(RegClass, RegNum);
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp444 unsigned RegNum; member in struct:__anon25988::ARMOperand::RegOp
449 unsigned RegNum; member in struct:__anon25988::ARMOperand::VectorListOp
478 unsigned RegNum; member in struct:__anon25988::ARMOperand::PostIdxRegOp
643 return Reg.RegNum;
1404 .contains(VectorList.RegNum));
1421 .contains(VectorList.RegNum));
1448 .contains(VectorList.RegNum));
1706 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; local
1707 Inst.addOperand(MCOperand::CreateReg(RegNum));
2121 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2512 CreateCCOut(unsigned RegNum, SMLoc S) argument
2529 CreateReg(unsigned RegNum, SMLoc S, SMLoc E) argument
2617 CreateVectorList(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
2631 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
2643 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
2693 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument
2890 unsigned RegNum = MatchRegisterName(lowerCase); local
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/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp2069 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); local
2073 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2074 // need to skip a register if RegNum is odd.
2075 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2076 State.AllocateReg(ArgRegs[RegNum]);
2097 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); local
2101 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2102 State.AllocateReg(ArgRegs[RegNum]);
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