Searched defs:SchedModel (Results 1 - 14 of 14) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h35 MCSchedModel SchedModel; member in class:llvm::TargetSchedModel
67 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
82 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
85 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
93 return SchedModel.getNumProcResourceKinds();
98 return SchedModel.getProcResource(PIdx);
105 return SchedModel.getProcResource(PIdx)->Name;
140 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
145 return SchedModel.getProcResource(PIdx)->BufferSize;
H A DScheduleDAGInstrs.h86 TargetSchedModel SchedModel; member in class:llvm::ScheduleDAGInstrs
171 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
175 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
176 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
H A DMachineTraceMetrics.h73 TargetSchedModel SchedModel; member in class:llvm::MachineTraceMetrics
111 /// This is an array with SchedModel.getNumProcResourceKinds() entries.
114 /// These numbers have already been scaled by SchedModel.getResourceFactor().
364 // where Kinds = SchedModel.getNumProcResourceKinds().
373 unsigned Factor = SchedModel.getLatencyFactor();
H A DMachineScheduler.h548 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
564 const TargetSchedModel *SchedModel; member in class:llvm::SchedBoundary
634 DAG(nullptr), SchedModel(nullptr), Rem(nullptr), Available(ID, Name+".A"),
683 return RetiredMOps * SchedModel->getMicroOpFactor();
691 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
822 const TargetSchedModel *SchedModel);
827 const TargetSchedModel *SchedModel; member in class:llvm::GenericSchedulerBase
833 Context(C), SchedModel(nullptr), TRI(nullptr) {}
/external/llvm/lib/MC/
H A DMCSubtargetInfo.cpp102 assert(Found->Value && "Missing processor SchedModel value");
108 const MCSchedModel *SchedModel = getSchedModelForCPU(CPU); local
109 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
/external/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp34 TargetSchedModel SchedModel; member in class:__anon25948::AArch64StorePairSuppress
84 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx);
126 SchedModel.init(*ST.getSchedModel(), &ST, TII);
133 if (!SchedModel.hasInstrSchedModel()) {
H A DAArch64ConditionalCompares.cpp726 const MCSchedModel *SchedModel; member in class:__anon25936::AArch64ConditionalCompares
848 unsigned DelayLimit = SchedModel->MispredictPenalty * 3 / 4;
896 SchedModel =
/external/llvm/include/llvm/MC/
H A DMCInstrItineraries.h113 const MCSchedModel *SchedModel; ///< Basic machine properties. member in class:llvm::InstrItineraryData
121 InstrItineraryData() : SchedModel(&MCSchedModel::DefaultSchedModel),
127 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
128 Itineraries(SchedModel->InstrItineraries) {}
/external/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.h47 const TargetSchedModel *SchedModel; member in class:llvm::VLIWResourceModel
58 SchedModel(SM), TotalPackets(0) {
65 Packet.resize(SchedModel->getIssueWidth());
135 const TargetSchedModel *SchedModel; member in struct:llvm::ConvergingVLIWScheduler::VLIWSchedBoundary
156 DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"),
169 SchedModel = smodel;
192 const TargetSchedModel *SchedModel; member in class:llvm::ConvergingVLIWScheduler
207 : DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
/external/llvm/lib/CodeGen/
H A DEarlyIfConversion.cpp583 const MCSchedModel *SchedModel; member in class:__anon25740::EarlyIfConverter
691 unsigned CritLimit = SchedModel->MispredictPenalty/2;
787 SchedModel =
H A DTargetInstrInfo.cpp749 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel, argument
754 return SchedModel->LoadLatency;
756 return SchedModel->HighLatency;
809 return defaultDefLatency(ItinData->SchedModel, DefMI);
852 defaultDefLatency(ItinData->SchedModel, DefMI));
H A DIfConversion.cpp159 TargetSchedModel SchedModel; member in class:__anon25750::IfConverter
280 SchedModel.init(*ST.getSchedModel(), &ST, TII);
687 unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
1585 unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
H A DMachineScheduler.cpp1597 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { argument
1599 if (!SchedModel->hasInstrSchedModel())
1601 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1605 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1606 * SchedModel->getMicroOpFactor();
1608 PI = SchedModel->getWriteProcResBegin(SC),
1609 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1611 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1621 SchedModel = smodel;
1623 if (SchedModel
2108 initResourceDelta(const ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) argument
[all...]
/external/llvm/lib/Target/ARM/
H A DARMSubtarget.h227 /// SchedModel - Processor specific instruction costs.
228 const MCSchedModel *SchedModel; member in class:llvm::ARMSubtarget

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