| /external/llvm/lib/Target/R600/ |
| H A D | SILowerI1Copies.cpp | 113 const TargetRegisterClass *SrcRC = local
117 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
130 SrcRC == &AMDGPU::VReg_1RegClass) {
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| H A D | SIFixSGPRCopies.cpp | 185 const TargetRegisterClass *SrcRC; local
192 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg);
193 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC);
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| H A D | SIInstrInfo.cpp | 1494 const TargetRegisterClass *SrcRC = Src.isReg() ? local
1501 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
1503 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1505 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
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| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.cpp | 40 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); local
42 if (DestRC != SrcRC)
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; local
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
171 if (MatchReg && SrcRC->getCopyCost() < 0) {
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| H A D | ScheduleDAGFast.cpp | 390 const TargetRegisterClass *SrcRC,
393 CopyFromSU->CopySrcRC = SrcRC;
398 CopyToSU->CopyDstRC = SrcRC;
388 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument
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| H A D | ScheduleDAGRRList.cpp | 1139 const TargetRegisterClass *SrcRC,
1142 CopyFromSU->CopySrcRC = SrcRC;
1147 CopyToSU->CopyDstRC = SrcRC;
1137 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument
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| /external/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 455 const TargetRegisterClass *SrcRC,
458 if (DefRC == SrcRC)
464 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
470 std::swap(DefRC, SrcRC);
475 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
477 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
569 const TargetRegisterClass *SrcRC = MRI->getRegClass(Src); local
572 ShouldRewrite = shareSameRegisterFile(TRI, DefRC, DefSubReg, SrcRC,
452 shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) argument
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| H A D | RegisterCoalescer.cpp | 290 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); local
299 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
306 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
310 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
313 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
328 CrossClass = NewRC != DstRC || NewRC != SrcRC;
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1931 const TargetRegisterClass *SrcRC = local
1938 unsigned NewVReg = MRI.createVirtualRegister(SrcRC);
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2134 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); local
2136 if (!SrcRC->contains(DstReg))
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| /external/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1053 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); local
1055 if (!SrcRC->contains(DstReg))
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