/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 35 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:llvm::AMDGPUMCCodeEmitter
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H A D | SIMCCodeEmitter.cpp | 62 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 172 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:SIMCCodeEmitter
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H A D | R600MCCodeEmitter.cpp | 49 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 170 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:R600MCCodeEmitter
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUCodeEmitter.h | 22 virtual uint64_t getMachineOpValue(const MachineInstr &MI, function in class:llvm::AMDGPUCodeEmitter
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 31 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:llvm::AMDGPUMCCodeEmitter
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H A D | SIMCCodeEmitter.cpp | 77 /// getMachineOpValue - Reutrn the encoding for an MCOperand. 78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 140 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:SIMCCodeEmitter 207 (getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK)
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H A D | R600MCCodeEmitter.cpp | 56 /// getMachineOpValue - Reutrn the encoding for an MCOperand. 57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 620 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:R600MCCodeEmitter
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUCodeEmitter.h | 22 virtual uint64_t getMachineOpValue(const MachineInstr &MI, function in class:llvm::AMDGPUCodeEmitter
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 31 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:llvm::AMDGPUMCCodeEmitter
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H A D | SIMCCodeEmitter.cpp | 77 /// getMachineOpValue - Reutrn the encoding for an MCOperand. 78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 140 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:SIMCCodeEmitter 207 (getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK)
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H A D | R600MCCodeEmitter.cpp | 56 /// getMachineOpValue - Reutrn the encoding for an MCOperand. 57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 620 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:R600MCCodeEmitter
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 79 /// getMachineOpValue - Return binary encoding of operand. If the machine 81 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 167 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 179 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 192 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 205 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 217 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 231 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; 235 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; 250 unsigned RegBits = getMachineOpValue(M 304 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:PPCMCCodeEmitter [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCCodeEmitter.cpp | 59 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr 60 unsigned getMachineOpValue(const MachineInstr &MI, 190 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 206 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 219 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 237 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16; 241 return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits; 253 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14; 257 return ((getMachineOpValue(MI, MO) >> 2) & 0x3FFF) | RegBits; 276 unsigned PPCCodeEmitter::getMachineOpValue(cons function in class:PPCCodeEmitter [all...] |
/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 53 /// getMachineOpValue - Return binary encoding of operand. If the machine 55 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 104 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI); 114 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:SparcMCCodeEmitter 146 return getMachineOpValue(MI, MO, Fixups, STI); 181 return getMachineOpValue(MI, MO, Fixups, STI); 194 return getMachineOpValue(MI, MO, Fixups, STI); 206 return getMachineOpValue(MI, MO, Fixups, STI);
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 50 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 117 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:SystemZMCCodeEmitter 131 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 132 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 141 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 142 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 151 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 152 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 153 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); 162 uint64_t Base = getMachineOpValue(M [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsCodeEmitter.cpp | 100 /// getMachineOpValue - Return binary encoding of operand. If the machine 102 unsigned getMachineOpValue(const MachineInstr &MI, 242 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16; 243 return (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits; 261 return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; 267 return getMachineOpValue(MI, MI.getOperand(OpNo-1)) + 268 getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; 289 /// getMachineOpValue - Return binary encoding of operand. If the machine 291 unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI, function in class:MipsCodeEmitter
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcCodeEmitter.cpp | 71 /// getMachineOpValue - Return binary encoding of operand. If the machine 73 unsigned getMachineOpValue(const MachineInstr &MI, 175 /// getMachineOpValue - Return binary encoding of operand. If the machine 177 unsigned SparcCodeEmitter::getMachineOpValue(const MachineInstr &MI, function in class:SparcCodeEmitter 198 return getMachineOpValue(MI, MO); 204 return getMachineOpValue(MI, MO); 210 return getMachineOpValue(MI, MO); 216 return getMachineOpValue(MI, MO);
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 53 /// getMachineOpValue - Return binary encoding of operand. If the machine 55 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 213 /// getMachineOpValue - Return binary encoding of operand. If the machine 216 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:AArch64MCCodeEmitter
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/external/llvm/lib/Target/ARM/ |
H A D | ARMCodeEmitter.cpp | 150 /// getMachineOpValue - Return binary encoding of operand. If the machine 152 unsigned getMachineOpValue(const MachineInstr &MI, 154 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { function in class:__anon25965::ARMCodeEmitter 155 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 160 // operand values, instead querying getMachineOpValue() directly for 440 /// getMachineOpValue - Return binary encoding of operand. If the machine 442 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, function in class:ARMCodeEmitter 698 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 713 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 736 Binary |= getMachineOpValue(M [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 72 /// getMachineOpValue - Return binary encoding of operand. If the machine 74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 506 /// getMachineOpValue - Return binary encoding of operand. If the machine 509 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:ARMMCCodeEmitter
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