Searched defs:tile_x (Results 1 - 25 of 31) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i915/
H A Dintel_span.c75 uint32_t tile_x = x / tile_width; local
83 + tile_x * tile_size
H A Dintel_fbo.c578 uint32_t *tile_x,
586 *tile_x = irb->draw_x & mask_x;
577 intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb, uint32_t *tile_x, uint32_t *tile_y) argument
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dbrw_blorp.cpp125 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x, argument
134 *tile_x = x_offset & mask_x;
H A Dgen7_misc_state.c109 uint32_t tile_x = 0, tile_y = 0; local
119 tile_x = draw_x & tile_mask_x;
129 * We have no guarantee that tile_x and tile_y are correctly aligned,
134 * tile_x and tile_y to 0. This is a temporary workaround until we
137 tile_x &= ~7;
142 dw3 = ((srb->Base.Base.Width + tile_x - 1) << 4) |
152 OUT_BATCH(tile_x | (tile_y << 16));
157 uint32_t tile_x, tile_y, offset; local
161 tile_x = draw_x & tile_mask_x;
171 * We have no guarantee that tile_x an
[all...]
H A Dintel_span.c75 uint32_t tile_x = x / tile_width; local
83 + tile_x * tile_size
H A Dbrw_misc_state.c372 uint32_t tile_x, tile_y; local
398 tile_x = draw_x & tile_mask_x;
408 * We have no guarantee that tile_x and tile_y are correctly aligned,
413 * tile_x and tile_y to 0. This is a temporary workaround until we come
417 tile_x &= ~7;
430 OUT_BATCH(((stencil_irb->Base.Base.Width + tile_x - 1) << 6) |
435 OUT_BATCH(tile_x | (tile_y << 16));
437 assert(tile_x == 0 && tile_y == 0);
446 uint32_t tile_x, tile_y, offset; local
456 tile_x
[all...]
H A Dgen7_wm_surface_state.c510 uint32_t tile_x, tile_y; local
552 surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
559 assert(tile_x % 4 == 0);
561 surf->ss5.x_offset = tile_x / 4;
H A Dgen7_blorp.cpp153 uint32_t tile_x, tile_y; local
171 surf->ss1.base_addr = surface->compute_tile_offsets(&tile_x, &tile_y);
177 assert(tile_x % 4 == 0);
179 surf->ss5.x_offset = tile_x / 4;
589 uint32_t tile_x = draw_x & tile_mask_x; local
603 * We have no guarantee that tile_x and tile_y are correctly aligned,
608 * tile_x and tile_y to 0. This is a temporary workaround until we come
611 tile_x &= ~7;
628 OUT_BATCH((params->depth.width + tile_x - 1) << 4 |
631 OUT_BATCH(tile_x |
[all...]
H A Dgen6_blorp.cpp427 uint32_t tile_x, tile_y; local
439 surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
461 assert(tile_x % 4 == 0);
463 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
841 uint32_t tile_x = draw_x & tile_mask_x; local
855 * We have no guarantee that tile_x and tile_y are correctly aligned,
860 * tile_x and tile_y to 0. This is a temporary workaround until we come
863 tile_x &= ~7;
884 (params->depth.width + tile_x - 1) << 6 |
887 OUT_BATCH(tile_x |
[all...]
H A Dintel_fbo.c578 uint32_t *tile_x,
586 *tile_x = irb->draw_x & mask_x;
577 intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb, uint32_t *tile_x, uint32_t *tile_y) argument
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/intel/
H A Dintel_span.c75 uint32_t tile_x = x / tile_width; local
83 + tile_x * tile_size
H A Dintel_fbo.c578 uint32_t *tile_x,
586 *tile_x = irb->draw_x & mask_x;
577 intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb, uint32_t *tile_x, uint32_t *tile_y) argument
/external/mesa3d/src/mesa/drivers/dri/i915/
H A Dintel_span.c75 uint32_t tile_x = x / tile_width; local
83 + tile_x * tile_size
H A Dintel_fbo.c578 uint32_t *tile_x,
586 *tile_x = irb->draw_x & mask_x;
577 intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb, uint32_t *tile_x, uint32_t *tile_y) argument
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_blorp.cpp125 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x, argument
134 *tile_x = x_offset & mask_x;
H A Dgen7_misc_state.c109 uint32_t tile_x = 0, tile_y = 0; local
119 tile_x = draw_x & tile_mask_x;
129 * We have no guarantee that tile_x and tile_y are correctly aligned,
134 * tile_x and tile_y to 0. This is a temporary workaround until we
137 tile_x &= ~7;
142 dw3 = ((srb->Base.Base.Width + tile_x - 1) << 4) |
152 OUT_BATCH(tile_x | (tile_y << 16));
157 uint32_t tile_x, tile_y, offset; local
161 tile_x = draw_x & tile_mask_x;
171 * We have no guarantee that tile_x an
[all...]
H A Dintel_span.c75 uint32_t tile_x = x / tile_width; local
83 + tile_x * tile_size
H A Dbrw_misc_state.c372 uint32_t tile_x, tile_y; local
398 tile_x = draw_x & tile_mask_x;
408 * We have no guarantee that tile_x and tile_y are correctly aligned,
413 * tile_x and tile_y to 0. This is a temporary workaround until we come
417 tile_x &= ~7;
430 OUT_BATCH(((stencil_irb->Base.Base.Width + tile_x - 1) << 6) |
435 OUT_BATCH(tile_x | (tile_y << 16));
437 assert(tile_x == 0 && tile_y == 0);
446 uint32_t tile_x, tile_y, offset; local
456 tile_x
[all...]
H A Dgen7_wm_surface_state.c510 uint32_t tile_x, tile_y; local
552 surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
559 assert(tile_x % 4 == 0);
561 surf->ss5.x_offset = tile_x / 4;
H A Dgen7_blorp.cpp153 uint32_t tile_x, tile_y; local
171 surf->ss1.base_addr = surface->compute_tile_offsets(&tile_x, &tile_y);
177 assert(tile_x % 4 == 0);
179 surf->ss5.x_offset = tile_x / 4;
589 uint32_t tile_x = draw_x & tile_mask_x; local
603 * We have no guarantee that tile_x and tile_y are correctly aligned,
608 * tile_x and tile_y to 0. This is a temporary workaround until we come
611 tile_x &= ~7;
628 OUT_BATCH((params->depth.width + tile_x - 1) << 4 |
631 OUT_BATCH(tile_x |
[all...]
H A Dgen6_blorp.cpp427 uint32_t tile_x, tile_y; local
439 surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
461 assert(tile_x % 4 == 0);
463 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
841 uint32_t tile_x = draw_x & tile_mask_x; local
855 * We have no guarantee that tile_x and tile_y are correctly aligned,
860 * tile_x and tile_y to 0. This is a temporary workaround until we come
863 tile_x &= ~7;
884 (params->depth.width + tile_x - 1) << 6 |
887 OUT_BATCH(tile_x |
[all...]
H A Dintel_fbo.c578 uint32_t *tile_x,
586 *tile_x = irb->draw_x & mask_x;
577 intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb, uint32_t *tile_x, uint32_t *tile_y) argument
/external/mesa3d/src/mesa/drivers/dri/intel/
H A Dintel_span.c75 uint32_t tile_x = x / tile_width; local
83 + tile_x * tile_size
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/llvmpipe/
H A Dlp_rast.c340 const unsigned tile_x = task->x, tile_y = task->y; local
367 tile_x + x, tile_y + y);
370 depth = lp_rast_get_depth_block_pointer(task, tile_x + x, tile_y + y);
375 tile_x + x, tile_y + y,
/external/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_rast.c340 const unsigned tile_x = task->x, tile_y = task->y; local
367 tile_x + x, tile_y + y);
370 depth = lp_rast_get_depth_block_pointer(task, tile_x + x, tile_y + y);
375 tile_x + x, tile_y + y,

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