Searched refs:Imm (Results 26 - 50 of 144) sorted by relevance

123456

/external/llvm/lib/Target/Mips/
H A DMips16InstrInfo.h87 int64_t Imm, MachineBasicBlock &MBB,
98 // build the proper one based on the Imm field
101 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
104 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
H A DMips16InstrInfo.cpp310 int64_t Imm, MachineBasicBlock &MBB,
326 int32_t lo = Imm & 0xFFFF;
391 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
446 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
447 if (validSpImm8(Imm))
454 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
456 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
309 loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, DebugLoc DL, unsigned &NewImm) const argument
H A DMipsSEInstrInfo.h77 unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp84 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
87 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
90 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
92 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
94 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
96 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
148 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
150 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
153 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
155 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
591 DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
600 DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
607 DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
623 DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument
630 DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument
647 DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument
687 DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm, unsigned Add) argument
693 DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm, unsigned Add) argument
699 DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
704 DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
710 DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
715 DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
721 DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
726 DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
732 DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
737 DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
742 DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
747 DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
752 DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
1470 unsigned Imm = fieldFromInstruction(insn, 10, 14); local
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp77 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
78 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
80 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
158 unsigned AArch64TTI::getIntImmCost(const APInt &Imm, Type *Ty) const { argument
166 APInt ImmVal = Imm;
168 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU);
183 const APInt &Imm, Type *Ty) const {
240 unsigned Cost = AArch64TTI::getIntImmCost(Imm, Ty);
244 return AArch64TTI::getIntImmCost(Imm, Ty);
248 const APInt &Imm, Typ
182 getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const argument
247 getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) const argument
[all...]
H A DAArch64ExpandPseudoInsts.cpp65 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { argument
68 return (Imm >> (ChunkIdx * 16)) & 0xFFFF;
73 static uint64_t replicateChunk(uint64_t Imm, unsigned FromIdx, unsigned ToIdx) { argument
78 const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt;
80 Imm &= ~(0xFFFFLL << ShiftAmt);
82 return Imm | Chunk;
245 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) {
250 Imm &= ~(Mask << (Idx * 16));
253 Imm |= Mask << (Idx * 16);
255 return Imm;
[all...]
/external/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp85 uint64_t Imm = MI.getOperand(1).getImm();
86 if (SystemZ::isImmLL(Imm)) {
91 if (SystemZ::isImmLH(Imm)) {
94 MI.getOperand(1).setImm(Imm >> 16);
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp65 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; local
66 switch (Imm) {
89 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; local
90 switch (Imm) {
129 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; local
130 switch (Imm) {
H A DX86IntelInstPrinter.cpp55 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; local
56 switch (Imm) {
79 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; local
80 switch (Imm) {
119 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; local
120 switch (Imm) {
/external/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp95 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
96 return PrevTTI->isLegalAddImmediate(Imm);
99 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
100 return PrevTTI->isLegalICmpImmediate(Imm);
148 unsigned TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const { argument
149 return PrevTTI->getIntImmCost(Imm, Ty);
153 const APInt &Imm, Type *Ty) const {
154 return PrevTTI->getIntImmCost(Opc, Idx, Imm, Ty);
158 const APInt &Imm, Type *Ty) const {
159 return PrevTTI->getIntImmCost(IID, Idx, Imm, T
152 getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const argument
157 getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) const argument
[all...]
/external/llvm/lib/IR/
H A DAutoUpgrade.cpp312 unsigned Imm; local
314 Imm = 0;
316 Imm = 1;
318 Imm = 2;
320 Imm = 3;
322 Imm = 4;
324 Imm = 5;
326 Imm = 6;
328 Imm = 7;
334 CI->getArgOperand(1), Builder.getInt8(Imm));
367 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); local
[all...]
/external/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp243 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
245 assert(isUInt<N>(Imm) && "Invalid immediate");
246 Inst.addOperand(MCOperand::CreateImm(Imm));
251 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
253 assert(isUInt<N>(Imm) && "Invalid immediate");
254 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
258 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
263 uint64_t Base = Imm >> 16;
264 uint64_t Disp = Imm & 0xFFFF;
293 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
[all...]
/external/llvm/utils/TableGen/
H A DPseudoLoweringEmitter.cpp28 enum MapKind { Operand, Imm, Reg }; enumerator in enum:__anon26603::PseudoLoweringEmitter::OpData::MapKind
32 uint64_t Imm; // Integer immedate value. member in union:__anon26603::PseudoLoweringEmitter::OpData::__anon26604
105 OperandMap[BaseIdx + i].Kind = OpData::Imm;
106 OperandMap[BaseIdx + i].Data.Imm = II->getValue();
234 case OpData::Imm:
236 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
H A DCodeGenInstruction.h307 int64_t Imm; member in struct:llvm::CodeGenInstAlias::ResultOperand
316 ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {}
325 int64_t getImm() const { assert(isImm()); return Imm; }
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.h77 inline SDValue getI32Imm(unsigned Imm) { argument
78 return CurDAG->getTargetConstant(Imm, MVT::i32);
/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp110 unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
114 uint64_t Imm);
157 unsigned PPCMaterialize32BitInt(int64_t Imm,
159 unsigned PPCMaterialize64BitInt(int64_t Imm,
716 uint64_t Imm = CI->getZExtValue(); local
717 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
748 long Imm = 0; local
757 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
758 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
1127 int Imm = (int)CIVal.getSExtValue(); local
1921 PPCMaterialize32BitInt(int64_t Imm, const TargetRegisterClass *RC) argument
1953 PPCMaterialize64BitInt(int64_t Imm, const TargetRegisterClass *RC) argument
2039 int64_t Imm = CI->getZExtValue(); local
2180 FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) argument
2217 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
[all...]
/external/llvm/lib/Target/SystemZ/InstPrinter/
H A DSystemZInstPrinter.cpp162 uint64_t Imm = MI->getOperand(OpNum).getImm(); local
163 assert(Imm > 0 && Imm < 15 && "Invalid condition");
164 O << CondNames[Imm - 1];
/external/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp410 uint64_t Imm = CI->getZExtValue(); local
415 isPowerOf2_64(Imm)) {
416 Imm = Log2_64(Imm);
422 isPowerOf2_64(Imm)) {
423 --Imm;
428 Op0IsKill, Imm, VT.getSimpleVT());
1249 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1261 uint64_t /*Imm*/) {
1276 uint64_t /*Imm*/) {
1284 FastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument
1425 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
1497 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
1551 FastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument
[all...]
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp603 unsigned Imm = MO.getImm();
605 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
622 unsigned Imm = MO.getImm();
624 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
742 unsigned Imm = MI->getOperand(OpNum).getImm();
743 if (Imm == 0)
745 assert(Imm > 0 && Imm < 3
[all...]
/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp107 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
109 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
111 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
930 unsigned X86TTI::getIntImmCost(const APInt &Imm, Type *Ty) const { argument
944 if (Imm == 0)
948 APInt ImmVal = Imm;
950 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU);
964 unsigned X86TTI::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, argument
1023 unsigned Cost = X86TTI::getIntImmCost(Imm, Ty);
1029 return X86TTI::getIntImmCost(Imm, T
1032 getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) const argument
[all...]
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp123 uint64_t Imm);
128 uint64_t Imm);
131 uint64_t Imm);
371 uint64_t Imm) {
382 .addImm(Imm));
386 .addImm(Imm));
398 uint64_t Imm) {
411 .addImm(Imm));
416 .addImm(Imm));
426 uint64_t Imm) {
368 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
394 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
424 FastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument
475 int Imm; local
532 unsigned Imm = (unsigned)~(CI->getSExtValue()); local
934 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; local
948 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; local
1310 uint64_t Imm = CI->getZExtValue(); local
1375 int Imm = 0; local
1638 int Imm = 0; local
2623 uint32_t Imm : 8; // All instructions have either a shift or a mask. member in struct:InstructionTable
2685 unsigned Imm = ITP->Imm; local
2914 const uint64_t Imm = MI->getOperand(2).getImm(); local
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DSIMCCodeEmitter.cpp245 } Imm; local
248 Imm.f = MO.getFPImm();
249 Value |= ((uint64_t)Imm.i) << 32;
/external/llvm/tools/llvm-readobj/
H A DARMWinEHPrinter.cpp238 uint8_t Imm = OC[Offset] & 0x7f; local
242 Imm);
328 uint16_t Imm = ((OC[Offset + 0] & 0x03) << 8) | ((OC[Offset + 1] & 0xff) << 0); local
333 Imm);
417 uint32_t Imm = (OC[Offset + 1] << 8) | (OC[Offset + 2] << 0); local
422 Imm);
430 uint32_t Imm = (OC[Offset + 1] << 16) local
437 static_cast<const char *>(Prologue ? "sub" : "add"), Imm);
445 uint32_t Imm = (OC[Offset + 1] << 8) | (OC[Offset + 2] << 0); local
450 static_cast<const char *>(Prologue ? "sub" : "add"), Imm);
458 uint32_t Imm = (OC[Offset + 1] << 16) local
[all...]
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DSIMCCodeEmitter.cpp245 } Imm; local
248 Imm.f = MO.getFPImm();
249 Value |= ((uint64_t)Imm.i) << 32;
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp86 unsigned &Reg, unsigned &Imm,
539 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
561 Imm = SImm;
1111 unsigned Imm = MO1.getImm(); local
1112 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1114 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1117 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1147 unsigned Imm = MO1.getImm(); local
1148 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1150 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
538 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1183 unsigned Imm = MO2.getImm(); local
[all...]

Completed in 1625 milliseconds

123456