Searched refs:getOperand (Results 51 - 75 of 529) sorted by relevance

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/external/llvm/lib/Target/Hexagon/InstPrinter/
H A DHexagonInstPrinter.cpp91 const MCOperand& MO = MI->getOperand(OpNo);
106 const MCOperand& MO = MI->getOperand(OpNo);
111 O << MI->getOperand(OpNo).getImm();
127 O << MI->getOperand(OpNo).getImm();
132 O << -MI->getOperand(OpNo).getImm();
142 const MCOperand& MO0 = MI->getOperand(OpNo);
143 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
151 const MCOperand& MO0 = MI->getOperand(OpNo);
152 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
159 assert(MI->getOperand(OpN
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/external/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp65 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
89 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
129 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
143 const MCOperand &Op = MI->getOperand(OpNo);
164 const MCOperand &Op = MI->getOperand(OpNo);
186 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
187 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
188 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
189 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
216 unsigned ScaleVal = MI->getOperand(O
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H A DX86IntelInstPrinter.cpp55 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
79 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
119 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
132 const MCOperand &Op = MI->getOperand(OpNo);
153 const MCOperand &Op = MI->getOperand(OpNo);
166 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
167 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
168 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
169 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
170 const MCOperand &SegReg = MI->getOperand(O
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/external/llvm/lib/Analysis/
H A DPHITransAddr.cpp35 isa<ConstantInt>(Inst->getOperand(1)))
40 // cerr << "OP:\t\t\t\t" << *PtrInst->getOperand(0);
83 if (!VerifySubExpr(I->getOperand(i), InstInputs))
140 if (Instruction *Op = dyn_cast<Instruction>(I->getOperand(i)))
181 if (Instruction *Op = dyn_cast<Instruction>(Inst->getOperand(i)))
191 Value *PHIIn = PHITranslateSubExpr(Cast->getOperand(0), CurBB, PredBB, DT);
193 if (PHIIn == Cast->getOperand(0))
220 Value *GEPOp = PHITranslateSubExpr(GEP->getOperand(i), CurBB, PredBB, DT);
223 AnyChanged |= GEPOp != GEP->getOperand(i);
248 if (GEPI->getOperand(
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H A DCostModel.cpp174 Value *L = BinOp->getOperand(0);
175 Value *R = BinOp->getOperand(1);
189 Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
190 Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
247 ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
254 BinaryOperator *RdxStart = dyn_cast<BinaryOperator>(ReduxRoot->getOperand(0));
258 Type *VecTy = ReduxRoot->getOperand(0)->getType();
293 Value *L = B->getOperand(0);
294 Value *R = B->getOperand(1);
310 ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(
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/external/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp254 const MachineOperand &MO = candidate->getOperand(i);
288 const MachineOperand &Reg = MI->getOperand(0);
293 const MachineOperand &RegOrImm = MI->getOperand(1);
309 const MachineOperand &MO = MI->getOperand(i);
353 const MachineOperand &MO = I->getOperand(structSizeOpNum);
369 unsigned reg = AddMI->getOperand(0).getReg();
382 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
397 unsigned reg = OrMI->getOperand(0).getReg();
403 && OrMI->getOperand(1).getReg() != SP::G0
404 && OrMI->getOperand(
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H A DSparcRegisterInfo.cpp106 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
107 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
128 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
129 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));
146 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
147 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
159 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
164 MI.getOperand(FIOperandNum + 1).getImm() +
178 unsigned SrcReg = MI.getOperand(2).getReg();
186 MI.getOperand(
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/external/llvm/lib/CodeGen/
H A DOptimizePHIs.cpp91 unsigned DstReg = MI->getOperand(0).getReg();
103 unsigned SrcReg = MI->getOperand(i).getReg();
110 !SrcMI->getOperand(0).getSubReg() &&
111 !SrcMI->getOperand(1).getSubReg() &&
112 TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
113 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
134 unsigned DstReg = MI->getOperand(0).getReg();
169 unsigned OldReg = MI->getOperand(0).getReg();
/external/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp202 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()))
208 NewMI.addOperand(MI->getOperand(i));
217 MI->getOperand(0).getReg(),
218 MI->getOperand(1).getReg());
226 MI->getOperand(0).getReg(),
227 MI->getOperand(1).getReg());
235 MI->getOperand(0).getReg(),
236 MI->getOperand(1).getReg());
242 unsigned maskedRegister = MI->getOperand(0).getReg();
250 TII->buildMovImm(*BB, I, MI->getOperand(
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp292 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
302 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
353 Op.getNode()->getOperand(0)),
355 Op.getNode()->getOperand(1)));
419 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
422 TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
425 return TLO.CombineTo(Op, Op.getOperand(0));
432 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
436 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
444 return TLO.CombineTo(Op, Op.getOperand(
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H A DLegalizeFloatTypes.cpp113 return BitConvertToInteger(N->getOperand(0));
127 BitConvertToInteger(N->getOperand(0)),
128 BitConvertToInteger(N->getOperand(1)));
138 SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
141 NewOp, N->getOperand(1));
152 SDValue Op = GetSoftenedFloat(N->getOperand(0));
158 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
159 GetSoftenedFloat(N->getOperand(1)) };
171 SDValue Op = GetSoftenedFloat(N->getOperand(0));
182 SDValue LHS = GetSoftenedFloat(N->getOperand(
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H A DLegalizeIntegerTypes.cpp159 SDValue Op = SExtPromotedInteger(N->getOperand(0));
161 Op.getValueType(), Op, N->getOperand(1));
166 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
168 Op.getValueType(), Op, N->getOperand(1));
185 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
201 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
212 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
220 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
221 SDValue Op3 = GetPromotedInteger(N->getOperand(
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H A DLegalizeVectorTypes.cpp136 SDValue LHS = GetScalarizedVector(N->getOperand(0));
137 SDValue RHS = GetScalarizedVector(N->getOperand(1));
143 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
144 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
145 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
159 NewVT, N->getOperand(0));
164 SDValue InOp = N->getOperand(0);
174 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
178 N->getOperand(3),
179 N->getOperand(
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/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineCompares.cpp238 !isa<ConstantInt>(GEP->getOperand(1)) ||
239 !cast<ConstantInt>(GEP->getOperand(1))->isZero() ||
240 isa<Constant>(GEP->getOperand(2)))
250 ConstantInt *Idx = dyn_cast<ConstantInt>(GEP->getOperand(i));
298 Constant *CompareRHS = cast<Constant>(ICI.getOperand(1));
385 Value *Idx = GEP->getOperand(2);
519 if (ConstantInt *CI = dyn_cast<ConstantInt>(GEP->getOperand(i))) {
540 Value *VariableIdx = GEP->getOperand(i);
547 ConstantInt *CI = dyn_cast<ConstantInt>(GEP->getOperand(i));
567 Type *IntPtrTy = DL.getIntPtrType(GEP->getOperand(
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H A DInstCombineSelect.cpp35 Value *CmpLHS = ICI->getOperand(0);
36 Value *CmpRHS = ICI->getOperand(1);
154 Type *FIOpndTy = FI->getOperand(0)->getType();
155 if (TI->getOperand(0)->getType() != FIOpndTy)
168 Value *NewSI = Builder->CreateSelect(SI.getCondition(), TI->getOperand(0),
169 FI->getOperand(0), SI.getName()+".v");
181 if (TI->getOperand(0) == FI->getOperand(0)) {
182 MatchOp = TI->getOperand(0);
183 OtherOpT = TI->getOperand(
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H A DInstCombineAndOrXor.cpp127 Value *X = Op->getOperand(0);
248 Value *ShVal = Op->getOperand(0);
337 !isa<ConstantInt>(LHSI->getOperand(1))) return nullptr;
339 ConstantInt *N = cast<ConstantInt>(LHSI->getOperand(1));
374 return Builder->CreateSub(LHSI->getOperand(0), RHS, "fold");
375 return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold");
508 ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1));
545 X = I->getOperand(0);
560 if (LHS->getOperand(0)->getType() != RHS->getOperand(
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp98 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
102 MI.getOperand(FIOperandNum + 1).getImm();
105 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
106 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
/external/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp165 if (MI->isCopy() && usesRegClass(MI->getOperand(1),
167 SReg = MI->getOperand(1).getReg();
193 MachineOperand &MO = MI->getOperand(i);
216 MachineOperand &MODef = Def->getOperand(j);
249 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
253 unsigned DPRReg = MI->getOperand(1).getReg();
254 unsigned SPRReg = MI->getOperand(2).getReg();
257 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
258 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
270 EC->getOperand(
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/external/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp119 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isReg());
121 unsigned DestReg = MI->getOperand(0).getReg();
122 unsigned SrcReg = MI->getOperand(1).getReg();
130 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
131 unsigned DestReg = MI->getOperand(0).getReg();
135 (ShouldCombineAggressively || isInt<8>(MI->getOperand(1).getImm()));
141 assert(MI->getOperand(0).isReg() && MI->getOperand(
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/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp70 const MCOperand &Op0 = MI->getOperand(0);
71 const MCOperand &Op1 = MI->getOperand(1);
72 const MCOperand &Op2 = MI->getOperand(2);
73 const MCOperand &Op3 = MI->getOperand(3);
164 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
165 const MCOperand &Op2 = MI->getOperand(2);
166 int ImmR = MI->getOperand(3).getImm();
167 int ImmS = MI->getOperand(4).getImm();
195 MI->getOperand(1).isExpr()) {
201 O << getRegisterName(MI->getOperand(
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/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp37 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
38 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
41 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
42 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
43 if (MI.getOperand(4).isImm() && MI.getOperand(
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/external/llvm/lib/Target/AArch64/
H A DAArch64AddressTypePromotion.cpp164 if (isa<TruncInst>(Inst) && isa<SExtInst>(Inst->getOperand(0))) {
165 const Instruction *Opnd = cast<Instruction>(Inst->getOperand(0));
168 Opnd->getOperand(0)->getType()->getIntegerBitWidth() &&
169 Inst->getOperand(0)->getType()->getIntegerBitWidth() <=
200 if (isa<BinaryOperator>(Inst) && isa<ConstantInt>(Inst->getOperand(1)))
270 while (auto *Inst = dyn_cast<Instruction>(SExt->getOperand(0))) {
293 SExt->setOperand(0, Inst->getOperand(0));
313 DEBUG(dbgs() << "Operand:\n" << *(Inst->getOperand(OpIdx)) << '\n');
314 if (Inst->getOperand(OpIdx)->getType() == SExt->getType() ||
320 Value *Opnd = Inst->getOperand(OpId
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H A DAArch64LoadStoreOptimizer.cpp293 MergeForward ? Paired->getOperand(1) : I->getOperand(1);
297 if (I->getOperand(2).getImm() ==
298 Paired->getOperand(2).getImm() + OffsetStride) {
306 int OffsetImm = RtMI->getOperand(2).getImm();
313 .addOperand(RtMI->getOperand(0))
314 .addOperand(Rt2MI->getOperand(0))
343 MachineOperand &MO = MI->getOperand(i);
395 unsigned Reg = FirstMI->getOperand(0).getReg();
396 unsigned BaseReg = FirstMI->getOperand(
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/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
90 unsigned SrcReg = MI.getOperand(OpNum).getReg();
91 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
102 assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
104 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
249 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
250 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
264 const MCOperand &BaseReg = MI.getOperand(O
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/external/llvm/include/llvm/IR/
H A DGetElementPtrTypeIterator.h59 return CT->getTypeAtIndex(getOperand());
66 Value *getOperand() const { return *OpIt; } function in class:llvm::generic_gep_type_iterator
70 CurTy = CT->getTypeAtIndex(getOperand());
87 (GEP->getOperand(0)->getType()->getScalarType(), GEP->op_begin()+1);
94 (GEP.getOperand(0)->getType()->getScalarType(), GEP.op_begin()+1);

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