Searched refs:reg (Results 101 - 125 of 1419) sorted by relevance

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/external/libunwind/src/arm/
H A DGresume.c119 int reg; local
123 for (reg = 0; reg <= UNW_REG_LAST; ++reg)
125 Debug (16, "copying %s %d\n", unw_regname (reg), reg);
126 if (unw_is_fpreg (reg))
128 if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0)
129 as->acc.access_fpreg (as, reg, &fpval, 1, arg);
133 if (tdep_access_reg (c, reg,
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/external/libunwind/src/hppa/
H A DGresume.c100 int reg; local
107 for (reg = 0; reg <= UNW_REG_LAST; ++reg)
109 Debug (16, "copying %s %d\n", unw_regname (reg), reg);
110 if (unw_is_fpreg (reg))
112 if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0)
113 (*access_fpreg) (as, reg, &fpval, 1, arg);
117 if (tdep_access_reg (c, reg,
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/external/llvm/lib/CodeGen/
H A DRegAllocBase.cpp89 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
92 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
94 LIS->removeInterval(VirtReg->reg);
105 << MRI->getRegClass(VirtReg->reg)->getName()
116 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
129 VRM->assignVirt2Phys(VirtReg->reg,
130 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
140 assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
141 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
143 LIS->removeInterval(SplitVirtReg->reg);
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/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_eu.h196 struct brw_reg reg; local
204 reg.type = type;
205 reg.file = file;
206 reg.nr = nr;
207 reg.subnr = subnr * type_sz(type);
208 reg.negate = 0;
209 reg.abs = 0;
210 reg.vstride = vstride;
211 reg.width = width;
212 reg
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H A Dbrw_vec4.cpp62 src_reg::src_reg(register_file file, int reg, const glsl_type *type) argument
67 this->reg = reg;
107 src_reg::src_reg(dst_reg reg) argument
111 this->file = reg.file;
112 this->reg = reg.reg;
113 this->reg_offset = reg.reg_offset;
114 this->type = reg
160 dst_reg(register_file file, int reg) argument
168 dst_reg(register_file file, int reg, const glsl_type *type, int writemask) argument
179 dst_reg(struct brw_reg reg) argument
187 dst_reg(src_reg reg) argument
307 int reg = inst->src[i].reg; local
323 int reg = inst->dst.reg; local
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H A Dbrw_wm_iz.c126 GLuint reg = 2; local
150 c->source_depth_reg = reg;
151 reg += 2;
158 c->aa_dest_stencil_reg = reg;
161 reg++;
165 c->dest_depth_reg = reg;
166 reg+=2;
169 c->nr_payload_regs = reg;
H A Dbrw_vec4_reg_allocate.cpp37 assign(unsigned int *reg_hw_locations, reg *reg) argument
39 if (reg->file == GRF) {
40 reg->reg = reg_hw_locations[reg->reg];
63 virtual_grf_used[inst->dst.reg] = true;
67 virtual_grf_used[inst->src[i].reg] = true;
121 int reg local
210 int reg = choose_spill_reg(g); local
226 int reg = ra_get_node_reg(g, i); local
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H A Dbrw_clip_util.c76 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1));
77 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0, 0, 1, 1));
78 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff, 0, 1));
79 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0, 1, 0, 1));
80 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff, 0, 0, 1));
81 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1, 0, 0, 1));
227 brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
237 allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
239 c->reg.R0,
263 c->reg
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dbrw_vec4.cpp62 src_reg::src_reg(register_file file, int reg, const glsl_type *type) argument
67 this->reg = reg;
107 src_reg::src_reg(dst_reg reg) argument
111 this->file = reg.file;
112 this->reg = reg.reg;
113 this->reg_offset = reg.reg_offset;
114 this->type = reg
160 dst_reg(register_file file, int reg) argument
168 dst_reg(register_file file, int reg, const glsl_type *type, int writemask) argument
179 dst_reg(struct brw_reg reg) argument
187 dst_reg(src_reg reg) argument
307 int reg = inst->src[i].reg; local
323 int reg = inst->dst.reg; local
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H A Dbrw_wm_iz.c126 GLuint reg = 2; local
150 c->source_depth_reg = reg;
151 reg += 2;
158 c->aa_dest_stencil_reg = reg;
161 reg++;
165 c->dest_depth_reg = reg;
166 reg+=2;
169 c->nr_payload_regs = reg;
H A Dbrw_vec4_reg_allocate.cpp37 assign(unsigned int *reg_hw_locations, reg *reg) argument
39 if (reg->file == GRF) {
40 reg->reg = reg_hw_locations[reg->reg];
63 virtual_grf_used[inst->dst.reg] = true;
67 virtual_grf_used[inst->src[i].reg] = true;
121 int reg local
210 int reg = choose_spill_reg(g); local
226 int reg = ra_get_node_reg(g, i); local
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H A Dbrw_clip_util.c76 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1));
77 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0, 0, 1, 1));
78 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff, 0, 1));
79 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0, 1, 0, 1));
80 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff, 0, 0, 1));
81 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1, 0, 0, 1));
227 brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
237 allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
239 c->reg.R0,
263 c->reg
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIRegisterInfo.h35 virtual unsigned getBinaryCode(unsigned reg) const;
37 /// getISARegClass - rc is an AMDIL reg class. This function returns the
44 unsigned getHWRegNum(unsigned reg) const;
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
H A Dradeon_cmdbuf.h20 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
21 #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
94 #define OUT_BATCH_REGVAL(reg, val) \
95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
100 #define OUT_BATCH_REGSEQ(reg, count) \
101 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
H A Dr200_fragshader.c328 GLuint reg; local
333 for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) {
334 if (shader->swizzlerq & (1 << (2 * reg)))
336 set_re_cntl_d3d( ctx, reg, 1);
338 else set_re_cntl_d3d( ctx, reg, 0);
364 for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
H A Dradeon_cmdbuf.h20 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
21 #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
94 #define OUT_BATCH_REGVAL(reg, val) \
95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
100 #define OUT_BATCH_REGSEQ(reg, count) \
101 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
/external/elfutils/0.153/libdw/
H A Ddwarf_frame_register.c81 const struct dwarf_frame_register *reg = &fs->regs[regno]; local
83 switch (reg->rule)
104 if (reg->value != 0)
106 .number = reg->value };
107 if (reg->rule == reg_val_offset)
115 .number = reg->value };
125 const uint8_t *p = fs->cache->data->d.d_buf + reg->value;
134 true, reg->rule == reg_val_expression,
/external/linux-tools-perf/perf-3.12.0/arch/arm/lib/
H A Dmemcpy.S19 .macro ldr1w ptr reg abort
20 W(ldr) \reg, [\ptr], #4
31 .macro ldr1b ptr reg cond=al abort
32 ldr\cond\()b \reg, [\ptr], #1
35 .macro str1w ptr reg abort
36 W(str) \reg, [\ptr], #4
43 .macro str1b ptr reg cond=al abort
44 str\cond\()b \reg, [\ptr], #1
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIRegisterInfo.h35 virtual unsigned getBinaryCode(unsigned reg) const;
37 /// getISARegClass - rc is an AMDIL reg class. This function returns the
44 unsigned getHWRegNum(unsigned reg) const;
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dradeon_cmdbuf.h20 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
21 #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
94 #define OUT_BATCH_REGVAL(reg, val) \
95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
100 #define OUT_BATCH_REGSEQ(reg, count) \
101 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
H A Dr200_fragshader.c328 GLuint reg; local
333 for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) {
334 if (shader->swizzlerq & (1 << (2 * reg)))
336 set_re_cntl_d3d( ctx, reg, 1);
338 else set_re_cntl_d3d( ctx, reg, 0);
364 for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg
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/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_cmdbuf.h20 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
21 #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
94 #define OUT_BATCH_REGVAL(reg, val) \
95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
100 #define OUT_BATCH_REGSEQ(reg, count) \
101 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
/external/libunwind/tests/
H A DGia64-test-stack.c59 int ret, reg, i, l; local
80 for (reg = 32; reg < 128; reg += 4)
85 ((ret = unw_get_reg (&c, UNW_IA64_GR + reg, &v0)) < 0
86 || (ret = unw_get_reg (&c, UNW_IA64_NAT + reg, &n0)) < 0
87 || (ret = unw_get_reg (&c, UNW_IA64_GR + reg + 1, &v1)) < 0
88 || (ret = unw_get_reg (&c, UNW_IA64_NAT + reg + 1, &n1)) < 0
89 || (ret = unw_get_reg (&c, UNW_IA64_GR + reg + 2, &v2)) < 0
90 || (ret = unw_get_reg (&c, UNW_IA64_NAT + reg
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/external/libunwind/src/ia64/
H A DGinit.c49 tdep_uc_addr (ucontext_t *uc, int reg, uint8_t *nat_bitnr) argument
51 return inlined_uc_addr (uc, reg, nat_bitnr);
126 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, argument
137 switch (reg)
140 if ((ret = __uc_get_grs (uc, (reg - UNW_IA64_GR), 1, &value, &nat)))
144 ret = __uc_set_grs (uc, (reg - UNW_IA64_GR), 1, val, nat);
150 if ((ret = __uc_get_grs (uc, (reg - UNW_IA64_GR), 1, &value, &nat)))
153 mask = 1 << (reg - UNW_IA64_GR);
161 ret = __uc_set_grs (uc, (reg - UNW_IA64_GR), 1, &value, nat);
168 if (reg
246 access_fpreg(unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, int write, void *arg) argument
281 access_reg(unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, void *arg) argument
334 access_fpreg(unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, int write, void *arg) argument
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/external/ltrace/sysdeps/linux-gnu/arm/
H A Dregs.c43 arm_get_register(struct process *proc, enum arm_register reg, uint32_t *lp) argument
46 long l = ptrace(PTRACE_PEEKUSER, proc->pid, (void *)(reg * 4L), 0);
54 arm_set_register(struct process *proc, enum arm_register reg, uint32_t lp) argument
57 (void *)(reg * 4L), (void *)lp);
61 arm_get_register_offpc(struct process *proc, enum arm_register reg, argument
64 if (arm_get_register(proc, reg, lp) < 0)
66 if (reg == ARM_REG_PC)
126 uint32_t reg; local
127 if (arm_get_register(proc, r, &reg) < 0)
131 return (arch_addr_t)(uintptr_t)reg;
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