/external/libunwind/src/x86/ |
H A D | Gget_save_loc.c | 29 unw_get_save_loc (unw_cursor_t *cursor, int reg, unw_save_loc_t *sloc) argument 36 switch (reg) 69 loc = x86_scratch_loc (c, reg); 105 loc = x86_scratch_loc (c, reg);
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/external/lldb/source/Plugins/Process/POSIX/ |
H A D | RegisterContext_x86_64.h | 152 GetRegisterSize(unsigned reg); 155 GetRegisterOffset(unsigned reg); 158 GetRegisterInfoAtIndex(size_t reg); 170 GetRegisterName(unsigned reg); 321 ReadRegister(const unsigned reg, lldb_private::RegisterValue &value); 324 WriteRegister(const unsigned reg, const lldb_private::RegisterValue &value); 336 bool CopyXSTATEtoYMM(uint32_t reg, lldb::ByteOrder byte_order); 337 bool CopyYMMtoXSTATE(uint32_t reg, lldb::ByteOrder byte_order); 338 bool IsFPR(unsigned reg, FPRType fpr_type);
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/external/mesa3d/src/gallium/drivers/r600/ |
H A D | r600_hw_context_priv.h | 52 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
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/external/openfst/src/script/ |
H A D | fst-class.cc | 57 typename IORegistration<FstT>::Register *reg = local 61 reg->GetReader(hdr.ArcType()); 116 IORegistration<VectorFstClass>::Register *reg = local 118 const IORegistration<VectorFstClass>::Entry &entry = reg->GetEntry(arc_type);
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/external/qemu/include/exec/ |
H A D | gdbstub.h | 30 typedef int (*gdb_reg_cb)(CPUArchState *env, uint8_t *buf, int reg);
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/external/skia/samplecode/ |
H A D | SampleBigBlur.cpp | 50 static SkViewRegister reg(MyFactory);
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/external/valgrind/main/coregrind/m_gdbserver/ |
H A D | regcache.h | 57 struct reg *find_register_by_number (int n);
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H A D | valgrind_low.h | 39 struct reg *reg_defs;
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/external/chromium_org/v8/src/mips/ |
H A D | disasm-mips.cc | 70 void PrintRegister(int reg); 138 void Decoder::PrintRegister(int reg) { argument 139 Print(converter_.NameOfCPURegister(reg)); 144 int reg = instr->RsValue(); local 145 PrintRegister(reg); 150 int reg = instr->RtValue(); local 151 PrintRegister(reg); 156 int reg = instr->RdValue(); local 157 PrintRegister(reg); 192 // Print the integer value of the rd field, when it is not used as reg 302 int reg = instr->RsValue(); local 306 int reg = instr->RtValue(); local 310 int reg = instr->RdValue(); local 324 int reg = instr->FsValue(); local 328 int reg = instr->FtValue(); local 332 int reg = instr->FdValue(); local 336 int reg = instr->FrValue(); local [all...] |
/external/chromium_org/v8/src/mips64/ |
H A D | disasm-mips64.cc | 70 void PrintRegister(int reg); 139 void Decoder::PrintRegister(int reg) { argument 140 Print(converter_.NameOfCPURegister(reg)); 145 int reg = instr->RsValue(); local 146 PrintRegister(reg); 151 int reg = instr->RtValue(); local 152 PrintRegister(reg); 157 int reg = instr->RdValue(); local 158 PrintRegister(reg); 193 // Print the integer value of the rd field, when it is not used as reg 303 int reg = instr->RsValue(); local 307 int reg = instr->RtValue(); local 311 int reg = instr->RdValue(); local 325 int reg = instr->FsValue(); local 329 int reg = instr->FtValue(); local 333 int reg = instr->FdValue(); local 337 int reg = instr->FrValue(); local [all...] |
/external/pcre/dist/sljit/ |
H A D | sljitNativeARM_T2_32.c | 516 sljit_si reg; local 527 reg = (flags & ARG2_IMM) ? arg1 : arg2; 546 if (!(flags & KEEP_FLAGS) && IS_2_LO_REGS(reg, dst)) { 548 return push_inst16(compiler, ADDSI3 | IMM3(imm) | RD3(dst) | RN3(reg)); 550 return push_inst16(compiler, SUBSI3 | IMM3(nimm) | RD3(dst) | RN3(reg)); 551 if (reg == dst) { 560 return push_inst32(compiler, ADDWI | RD4(dst) | RN4(reg) | IMM12(imm)); 562 return push_inst32(compiler, SUBWI | RD4(dst) | RN4(reg) | IMM12(nimm)); 566 return push_inst32(compiler, ADD_WI | (flags & SET_FLAGS) | RD4(dst) | RN4(reg) | imm); 571 return push_inst32(compiler, ADCI | (flags & SET_FLAGS) | RD4(dst) | RN4(reg) | im 870 emit_set_delta(struct sljit_compiler *compiler, sljit_si dst, sljit_si reg, sljit_sw value) argument 891 getput_arg_fast(struct sljit_compiler *compiler, sljit_si flags, sljit_si reg, sljit_si arg, sljit_sw argw) argument 1002 getput_arg(struct sljit_compiler *compiler, sljit_si flags, sljit_si reg, sljit_si arg, sljit_sw argw, sljit_si next_arg, sljit_sw next_argw) argument 1110 emit_op_mem(struct sljit_compiler *compiler, sljit_si flags, sljit_si reg, sljit_si arg, sljit_sw argw) argument 1119 emit_op_mem2(struct sljit_compiler *compiler, sljit_si flags, sljit_si reg, sljit_si arg1, sljit_sw arg1w, sljit_si arg2, sljit_sw arg2w) argument 1508 sljit_get_register_index(sljit_si reg) argument 1514 sljit_get_float_register_index(sljit_si reg) argument 1548 emit_fop_mem(struct sljit_compiler *compiler, sljit_si flags, sljit_si reg, sljit_si arg, sljit_sw argw) argument [all...] |
/external/lldb/tools/debugserver/source/MacOSX/arm/ |
H A D | DNBArchImpl.cpp | 1285 #define GPR_OFFSET_NAME(reg) (offsetof (DNBArchMachARM::GPR, __##reg)) 1287 #define EXC_OFFSET(reg) (offsetof (DNBArchMachARM::EXC, __##reg) + offsetof (DNBArchMachARM::Context, exc)) 1293 #define DEFINE_GPR_IDX(idx, reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_IDX(idx), gcc_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, NULL} 1294 #define DEFINE_GPR_NAME(reg, al 1511 GetRegisterValue(int set, int reg, DNBRegisterValue *value) argument 1609 SetRegisterValue(int set, int reg, const DNBRegisterValue *value) argument [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
H A D | brw_wm_fp.c | 84 struct prog_src_register reg; local 85 reg.File = file; 86 reg.Index = idx; 87 reg.Swizzle = SWIZZLE_NOOP; 88 reg.RelAddr = 0; 89 reg.Negate = NEGATE_NONE; 90 reg.Abs = 0; 91 reg.HasIndex2 = 0; 92 reg.RelAddr2 = 0; 93 reg 112 src_swizzle( struct prog_src_register reg, int x, int y, int z, int w ) argument 118 src_swizzle1( struct prog_src_register reg, int x ) argument 123 src_swizzle4( struct prog_src_register reg, uint swizzle ) argument 136 struct prog_dst_register reg; local 147 dst_mask( struct prog_dst_register reg, int mask ) argument 537 struct prog_src_register reg; local [all...] |
H A D | brw_eu_emit.c | 45 struct brw_reg reg) 47 if (reg.width == BRW_WIDTH_8 && p->compressed) 50 insn->header.execution_size = reg.width; /* note - definitions are compatible */ 85 gen7_convert_mrf_to_grf(struct brw_compile *p, struct brw_reg *reg) argument 96 if (intel->gen == 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) { 97 reg->file = BRW_GENERAL_REGISTER_FILE; 98 reg->nr += GEN7_MRF_HACK_START; 160 validate_reg(struct brw_instruction *insn, struct brw_reg reg) argument 168 if (reg.file == BRW_IMMEDIATE_VALUE) { 173 if (reg 43 guess_execution_size(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) argument 236 brw_set_src0(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) argument 314 brw_set_src1(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) argument 754 get_3src_subreg_nr(struct brw_reg reg) argument 2408 struct brw_reg reg = vec8(offset(dest, response_length-1)); local [all...] |
H A D | brw_vec4.h | 58 class reg class in namespace:brw 63 /** virtual register number. 0 = fixed hw reg */ 64 int reg; member in class:brw::reg 79 class src_reg : public reg 96 src_reg(register_file file, int reg, const glsl_type *type); 108 explicit src_reg(dst_reg reg); 117 class dst_reg : public reg 135 dst_reg(register_file file, int reg); 136 dst_reg(register_file file, int reg, const glsl_type *type, int writemask); 137 dst_reg(struct brw_reg reg); [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_wm_fp.c | 84 struct prog_src_register reg; local 85 reg.File = file; 86 reg.Index = idx; 87 reg.Swizzle = SWIZZLE_NOOP; 88 reg.RelAddr = 0; 89 reg.Negate = NEGATE_NONE; 90 reg.Abs = 0; 91 reg.HasIndex2 = 0; 92 reg.RelAddr2 = 0; 93 reg 112 src_swizzle( struct prog_src_register reg, int x, int y, int z, int w ) argument 118 src_swizzle1( struct prog_src_register reg, int x ) argument 123 src_swizzle4( struct prog_src_register reg, uint swizzle ) argument 136 struct prog_dst_register reg; local 147 dst_mask( struct prog_dst_register reg, int mask ) argument 537 struct prog_src_register reg; local [all...] |
H A D | brw_eu_emit.c | 45 struct brw_reg reg) 47 if (reg.width == BRW_WIDTH_8 && p->compressed) 50 insn->header.execution_size = reg.width; /* note - definitions are compatible */ 85 gen7_convert_mrf_to_grf(struct brw_compile *p, struct brw_reg *reg) argument 96 if (intel->gen == 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) { 97 reg->file = BRW_GENERAL_REGISTER_FILE; 98 reg->nr += GEN7_MRF_HACK_START; 160 validate_reg(struct brw_instruction *insn, struct brw_reg reg) argument 168 if (reg.file == BRW_IMMEDIATE_VALUE) { 173 if (reg 43 guess_execution_size(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) argument 236 brw_set_src0(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) argument 314 brw_set_src1(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) argument 754 get_3src_subreg_nr(struct brw_reg reg) argument 2408 struct brw_reg reg = vec8(offset(dest, response_length-1)); local [all...] |
H A D | brw_vec4.h | 58 class reg class in namespace:brw 63 /** virtual register number. 0 = fixed hw reg */ 64 int reg; member in class:brw::reg 79 class src_reg : public reg 96 src_reg(register_file file, int reg, const glsl_type *type); 108 explicit src_reg(dst_reg reg); 117 class dst_reg : public reg 135 dst_reg(register_file file, int reg); 136 dst_reg(register_file file, int reg, const glsl_type *type, int writemask); 137 dst_reg(struct brw_reg reg); [all...] |
/external/aac/libFDK/src/ |
H A D | FDK_crc.cpp | 196 const INT reg 260 int reg = hCrcInfo->regStart; local 262 FDK_ASSERT(hCrcInfo->crcRegData[reg].isActive==0); 263 hCrcInfo->crcRegData[reg].isActive = 1; 264 hCrcInfo->crcRegData[reg].maxBits = mBits; 265 hCrcInfo->crcRegData[reg].validBits = FDKgetValidBits(hBs) ; 266 hCrcInfo->crcRegData[reg].bitBufCntBits = 0; 270 return (reg); 276 const INT reg 279 FDK_ASSERT((reg [all...] |
/external/chromium_org/v8/src/x87/ |
H A D | lithium-codegen-x87.h | 84 void X87Mov(X87Register reg, Operand src, 86 void X87Mov(Operand src, X87Register reg, 88 void X87Mov(X87Register reg, X87Register src, 94 void X87LoadForUsage(X87Register reg); 96 void X87PrepareToWrite(X87Register reg) { x87_stack_.PrepareToWrite(reg); } argument 97 void X87CommitWrite(X87Register reg) { x87_stack_.CommitWrite(reg); } argument 99 void X87Fxch(X87Register reg, int other_slot = 0) { argument 100 x87_stack_.Fxch(reg, other_slo 102 X87Free(X87Register reg) argument 413 st(X87Register reg) argument 418 push(X87Register reg) argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | LiveRangeEdit.cpp | 171 for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) { 208 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second) 217 DefMI->addRegisterDead(LI->reg, nullptr); 287 TheDelegate->LRE_WillShrinkVirtReg(LI.reg); 349 TheDelegate->LRE_WillShrinkVirtReg(LI->reg); 359 if (LI->reg == RegsBeingSpilled[i]) { 374 bool IsOriginal = VRM && VRM->getOriginal(LI->reg) == LI->reg; 378 Dups.push_back(&createEmptyIntervalFrom(LI->reg)); 383 VRM->setIsSplitFromReg(Dups.back()->reg, [all...] |
/external/llvm/lib/Target/R600/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 43 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) { argument 44 switch (reg) { 64 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) { 67 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) { 70 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) { 73 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) { 76 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) { 79 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) { 82 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) { 85 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) { [all...] |
/external/libunwind/src/ia64/ |
H A D | Gresume.c | 185 int reg; local 195 # define MEMIFY(preg, reg) \ 199 tdep_uc_addr(c->as_arg, (reg), \ 243 for (reg = 0; reg <= UNW_REG_LAST; ++reg) 245 if (unw_is_fpreg (reg)) 247 if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0) 248 (*access_fpreg) (c->as, reg, &fpval, 1, c->as_arg); 252 if (tdep_access_reg (c, reg, [all...] |
H A D | Gscript.c | 43 IA64_INSN_MOVE_SCRATCH, /* s[dst] = scratch reg "val" */ 402 if (sr->curr.reg[r].where == IA64_WHERE_NONE 403 || sr->curr.reg[r].when >= sr->when_target) 416 max_when = sr->curr.reg[max_reg].when; 419 if (sr->curr.reg[regorder[j]].when > max_when) 423 max_when = sr->curr.reg[max_reg].when; 454 if (sr.when_target > sr.curr.reg[IA64_REG_PSP].when 455 && (sr.curr.reg[IA64_REG_PSP].where == IA64_WHERE_NONE) 456 && sr.curr.reg[IA64_REG_PSP].val != 0) 460 insn.val = sr.curr.reg[IA64_REG_PS [all...] |
/external/qemu/target-i386/ |
H A D | translate.c | 347 static inline bool byte_reg_is_xH(int reg) argument 349 if (reg < 4) { 353 if (reg >= 8 || x86_64_hregs) { 360 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) argument 364 if (!byte_reg_is_xH(reg)) { 365 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUX86State, regs[reg]) + REG_B_OFFSET); 367 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUX86State, regs[reg - 4]) + REG_H_OFFSET); 371 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUX86State, regs[reg]) + REG_W_OFFSET); 375 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUX86State, regs[reg]) + REG_L_OFFSET); 378 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, regs[reg]) 393 gen_op_mov_reg_T0(int ot, int reg) argument 398 gen_op_mov_reg_T1(int ot, int reg) argument 403 gen_op_mov_reg_A0(int size, int reg) argument 429 gen_op_mov_v_reg(int ot, TCGv t0, int reg) argument 438 gen_op_mov_TN_reg(int ot, int t_index, int reg) argument 443 gen_op_movl_A0_reg(int reg) argument 483 gen_op_add_reg_im(int size, int reg, int32_t val) argument 509 gen_op_add_reg_T0(int size, int reg) argument 535 gen_op_addl_A0_reg_sN(int shift, int reg) argument 546 gen_op_movl_A0_seg(int reg) argument 551 gen_op_addl_A0_seg(DisasContext *s, int reg) argument 561 gen_op_movq_A0_seg(int reg) argument 566 gen_op_addq_A0_seg(int reg) argument 572 gen_op_movq_A0_reg(int reg) argument 577 gen_op_addq_A0_reg_sN(int shift, int reg) argument 774 gen_extu(int ot, TCGv reg) argument 779 gen_exts(int ot, TCGv reg) argument 919 gen_compute_eflags_c(DisasContext *s, TCGv reg, bool inv) argument 1017 gen_compute_eflags_p(DisasContext *s, TCGv reg) argument 1025 gen_compute_eflags_s(DisasContext *s, TCGv reg, bool inv) argument 1049 gen_compute_eflags_o(DisasContext *s, TCGv reg) argument 1057 gen_compute_eflags_z(DisasContext *s, TCGv reg, bool inv) argument 1079 gen_setcc_slow(DisasContext *s, int jcc_op, TCGv reg, bool inv) argument 2403 gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, int ot, int reg, int is_store) argument 3287 int modrm, mod, rm, reg, reg_addr, offset_addr; local 4273 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val; local [all...] |