Searched refs:src0 (Results 26 - 50 of 144) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_fs.h146 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
147 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
149 fs_reg src0, fs_reg src1,fs_reg src2);
221 fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
222 fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
224 fs_reg src0, fs_reg src1, fs_reg src2);
277 struct brw_reg src0,
284 struct brw_reg src0,
316 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
317 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_re
[all...]
H A Dbrw_wm_fp.c207 struct prog_src_register src0,
226 inst->SrcReg[0] = src0;
237 struct prog_src_register src0,
243 src0, src1, src2);
559 struct prog_src_register src0 = inst->SrcReg[0]; local
565 /* dst.y = mul src0.y, src1.y
571 src0,
578 GLuint z = GET_SWZ(src0.Swizzle, Z);
580 /* dst.xz = swz src0.1zzz
586 src_swizzle(src0, SWIZZLE_ON
200 emit_tex_op(struct brw_wm_compile *c, GLuint op, struct prog_dst_register dest, GLuint saturate, GLuint tex_src_unit, GLuint tex_src_target, GLuint tex_shadow, struct prog_src_register src0, struct prog_src_register src1, struct prog_src_register src2 ) argument
233 emit_op(struct brw_wm_compile *c, GLuint op, struct prog_dst_register dest, GLuint saturate, struct prog_src_register src0, struct prog_src_register src1, struct prog_src_register src2 ) argument
623 struct prog_src_register src0 = inst->SrcReg[0]; local
688 struct prog_src_register src0 = inst->SrcReg[0]; local
925 struct prog_src_register src0 = inst->SrcReg[0]; local
[all...]
H A Dbrw_fs_emit.cpp170 struct brw_reg src0)
175 0, src0,
183 struct brw_reg src0,
187 brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1);
193 struct brw_reg src0)
202 0, src0,
210 0, sechalf(src0),
220 struct brw_reg src0,
228 brw_math2(p, dst, op, src0, src1);
232 brw_math2(p, sechalf(dst), op, sechalf(src0), sechal
168 generate_math1_gen7(fs_inst *inst, struct brw_reg dst, struct brw_reg src0) argument
181 generate_math2_gen7(fs_inst *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) argument
191 generate_math1_gen6(fs_inst *inst, struct brw_reg dst, struct brw_reg src0) argument
218 generate_math2_gen6(fs_inst *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) argument
457 struct brw_reg src0 = brw_reg(src.file, src.nr, 1, local
480 struct brw_reg src0 = brw_reg(src.file, src.nr, 0, local
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H A Dbrw_vec4_visitor.cpp35 src_reg src0, src_reg src1, src_reg src2)
39 this->src[0] = src0;
67 src_reg src0, src_reg src1, src_reg src2)
70 src0, src1, src2));
75 vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1) argument
77 return emit(new(mem_ctx) vec4_instruction(this, opcode, dst, src0, src1));
81 vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0) argument
83 return emit(new(mem_ctx) vec4_instruction(this, opcode, dst, src0));
94 vec4_visitor::op(dst_reg dst, src_reg src0) \
97 src0); \
33 vec4_instruction(vec4_visitor *v, enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1, src_reg src2) argument
66 emit(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1, src_reg src2) argument
137 IF(src_reg src0, src_reg src1, uint32_t condition) argument
159 CMP(dst_reg dst, src_reg src0, src_reg src1, uint32_t condition) argument
209 emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements) argument
283 emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1) argument
320 emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1) argument
329 emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1) argument
987 emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1) argument
[all...]
H A Dbrw_fs.cpp87 fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0) argument
92 this->src[0] = src0;
100 fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1) argument
105 this->src[0] = src0;
117 fs_reg src0, fs_reg src1, fs_reg src2)
122 this->src[0] = src0;
336 fs_visitor::emit(enum opcode opcode, fs_reg dst, fs_reg src0) argument
338 return emit(fs_inst(opcode, dst, src0));
342 fs_visitor::emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1) argument
344 return emit(fs_inst(opcode, dst, src0, src
116 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) argument
348 emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) argument
831 emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1) argument
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/external/chromium_org/native_client_sdk/src/examples/demo/life/
H A Dlife.c243 uint8_t *src0 = (g_Context.cell_in + (y - 1) * desc.size.width) + 1; local
244 uint8_t *src1 = src0 + desc.size.width;
253 count = src0[-1] + src0[0] + src0[1] +
262 ++src0;
/external/chromium_org/native_client_sdk/src/gonacl_appengine/src/life/
H A Dlife.c243 uint8_t *src0 = (g_Context.cell_in + (y - 1) * desc.size.width) + 1; local
244 uint8_t *src1 = src0 + desc.size.width;
253 count = src0[-1] + src0[0] + src0[1] +
260 ++src0;
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_info.c272 struct lp_tgsi_channel_info src0; local
275 analyse_src(ctx, &src0, &inst->Src[0].Register, chan);
278 if (is_immediate(&src0, 0.0f)) {
279 res[chan] = src0;
282 } else if (is_immediate(&src0, 1.0f)) {
285 res[chan] = src0;
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/
H A Di915_fpc_emit.c116 uint saturate, uint src0, uint src1, uint src2)
125 if (GET_UREG_TYPE(src0) == REG_TYPE_CONST)
140 s[0] = src0;
156 src0 = s[0];
163 *(p->csr++) = (op | A0_DEST(dest) | mask | saturate | A0_SRC0(src0));
164 *(p->csr++) = (A1_SRC0(src0) | A1_SRC1(src1));
228 coord, 0, 0 ); /* src0, src1, src2 */
112 i915_emit_arith(struct i915_fp_compile * p, uint op, uint dest, uint mask, uint saturate, uint src0, uint src1, uint src2) argument
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_info.c272 struct lp_tgsi_channel_info src0; local
275 analyse_src(ctx, &src0, &inst->Src[0].Register, chan);
278 if (is_immediate(&src0, 0.0f)) {
279 res[chan] = src0;
282 } else if (is_immediate(&src0, 1.0f)) {
285 res[chan] = src0;
/external/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_emit.c116 uint saturate, uint src0, uint src1, uint src2)
125 if (GET_UREG_TYPE(src0) == REG_TYPE_CONST)
140 s[0] = src0;
156 src0 = s[0];
163 *(p->csr++) = (op | A0_DEST(dest) | mask | saturate | A0_SRC0(src0));
164 *(p->csr++) = (A1_SRC0(src0) | A1_SRC1(src1));
228 coord, 0, 0 ); /* src0, src1, src2 */
112 i915_emit_arith(struct i915_fp_compile * p, uint op, uint dest, uint mask, uint saturate, uint src0, uint src1, uint src2) argument
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dbrw_wm_fp.c207 struct prog_src_register src0,
226 inst->SrcReg[0] = src0;
237 struct prog_src_register src0,
243 src0, src1, src2);
559 struct prog_src_register src0 = inst->SrcReg[0]; local
565 /* dst.y = mul src0.y, src1.y
571 src0,
578 GLuint z = GET_SWZ(src0.Swizzle, Z);
580 /* dst.xz = swz src0.1zzz
586 src_swizzle(src0, SWIZZLE_ON
200 emit_tex_op(struct brw_wm_compile *c, GLuint op, struct prog_dst_register dest, GLuint saturate, GLuint tex_src_unit, GLuint tex_src_target, GLuint tex_shadow, struct prog_src_register src0, struct prog_src_register src1, struct prog_src_register src2 ) argument
233 emit_op(struct brw_wm_compile *c, GLuint op, struct prog_dst_register dest, GLuint saturate, struct prog_src_register src0, struct prog_src_register src1, struct prog_src_register src2 ) argument
623 struct prog_src_register src0 = inst->SrcReg[0]; local
688 struct prog_src_register src0 = inst->SrcReg[0]; local
925 struct prog_src_register src0 = inst->SrcReg[0]; local
[all...]
H A Dbrw_fs_emit.cpp170 struct brw_reg src0)
175 0, src0,
183 struct brw_reg src0,
187 brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1);
193 struct brw_reg src0)
202 0, src0,
210 0, sechalf(src0),
220 struct brw_reg src0,
228 brw_math2(p, dst, op, src0, src1);
232 brw_math2(p, sechalf(dst), op, sechalf(src0), sechal
168 generate_math1_gen7(fs_inst *inst, struct brw_reg dst, struct brw_reg src0) argument
181 generate_math2_gen7(fs_inst *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) argument
191 generate_math1_gen6(fs_inst *inst, struct brw_reg dst, struct brw_reg src0) argument
218 generate_math2_gen6(fs_inst *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) argument
457 struct brw_reg src0 = brw_reg(src.file, src.nr, 1, local
480 struct brw_reg src0 = brw_reg(src.file, src.nr, 0, local
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H A Dbrw_vec4_visitor.cpp35 src_reg src0, src_reg src1, src_reg src2)
39 this->src[0] = src0;
67 src_reg src0, src_reg src1, src_reg src2)
70 src0, src1, src2));
75 vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1) argument
77 return emit(new(mem_ctx) vec4_instruction(this, opcode, dst, src0, src1));
81 vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0) argument
83 return emit(new(mem_ctx) vec4_instruction(this, opcode, dst, src0));
94 vec4_visitor::op(dst_reg dst, src_reg src0) \
97 src0); \
33 vec4_instruction(vec4_visitor *v, enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1, src_reg src2) argument
66 emit(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1, src_reg src2) argument
137 IF(src_reg src0, src_reg src1, uint32_t condition) argument
159 CMP(dst_reg dst, src_reg src0, src_reg src1, uint32_t condition) argument
209 emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements) argument
283 emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1) argument
320 emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1) argument
329 emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1) argument
987 emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1) argument
[all...]
H A Dbrw_fs.cpp87 fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0) argument
92 this->src[0] = src0;
100 fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1) argument
105 this->src[0] = src0;
117 fs_reg src0, fs_reg src1, fs_reg src2)
122 this->src[0] = src0;
336 fs_visitor::emit(enum opcode opcode, fs_reg dst, fs_reg src0) argument
338 return emit(fs_inst(opcode, dst, src0));
342 fs_visitor::emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1) argument
344 return emit(fs_inst(opcode, dst, src0, src
116 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) argument
348 emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) argument
831 emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1) argument
[all...]
H A Dbrw_eu.h833 struct brw_reg src0);
838 struct brw_reg src0, \
844 struct brw_reg src0, \
849 void brw_##OP(struct brw_compile *p, struct brw_reg dest, struct brw_reg src0);
925 struct brw_reg src0,
938 struct brw_reg src0,
946 struct brw_reg src0,
953 struct brw_reg src0,
964 struct brw_reg src0,
993 struct brw_reg src0,
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/
H A Dnv50_ir_from_tgsi.cpp1439 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1442 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1445 src0 = fetchSrc(0, c);
1447 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1730 Value *src0, *src1, *src2;
1776 src0 = fetchSrc(0, c);
1778 mkOp2(op, dstTy, dst0[c], src0, src1);
1785 src0 = fetchSrc(0, c);
1788 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
1806 src0
[all...]
H A Dnv50_ir_build_util.cpp79 Value *src0, Value *src1)
84 insn->setSrc(0, src0);
93 Value *src0, Value *src1, Value *src2)
98 insn->setSrc(0, src0);
224 Value *src0, Value *src1, Value *src2)
232 insn->setSrc(0, src0);
261 BuildUtil::mkQuadop(uint8_t q, Value *def, uint8_t l, Value *src0, Value *src1) argument
263 Instruction *quadop = mkOp2(OP_QUADOP, TYPE_F32, def, src0, src1);
78 mkOp2(operation op, DataType ty, Value *dst, Value *src0, Value *src1) argument
92 mkOp3(operation op, DataType ty, Value *dst, Value *src0, Value *src1, Value *src2) argument
223 mkCmp(operation op, CondCode cc, DataType ty, Value *dst, Value *src0, Value *src1, Value *src2) argument
/external/mesa3d/src/gallium/drivers/nv50/codegen/
H A Dnv50_ir_from_tgsi.cpp1439 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1442 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1445 src0 = fetchSrc(0, c);
1447 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1730 Value *src0, *src1, *src2;
1776 src0 = fetchSrc(0, c);
1778 mkOp2(op, dstTy, dst0[c], src0, src1);
1785 src0 = fetchSrc(0, c);
1788 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
1806 src0
[all...]
H A Dnv50_ir_build_util.cpp79 Value *src0, Value *src1)
84 insn->setSrc(0, src0);
93 Value *src0, Value *src1, Value *src2)
98 insn->setSrc(0, src0);
224 Value *src0, Value *src1, Value *src2)
232 insn->setSrc(0, src0);
261 BuildUtil::mkQuadop(uint8_t q, Value *def, uint8_t l, Value *src0, Value *src1) argument
263 Instruction *quadop = mkOp2(OP_QUADOP, TYPE_F32, def, src0, src1);
78 mkOp2(operation op, DataType ty, Value *dst, Value *src0, Value *src1) argument
92 mkOp3(operation op, DataType ty, Value *dst, Value *src0, Value *src1, Value *src2) argument
223 mkCmp(operation op, CondCode cc, DataType ty, Value *dst, Value *src0, Value *src1, Value *src2) argument
/external/qemu/distrib/sdl-1.2.15/src/audio/dc/
H A DSDL_dcaudio.c108 static void spu_memload_stereo8(int leftpos,int rightpos,void *src0,size_t size) argument
110 uint8 *src = src0;
130 static void spu_memload_stereo16(int leftpos,int rightpos,void *src0,size_t size) argument
132 uint16 *src = src0;
/external/chromium_org/native_client_sdk/src/examples/demo/life_simd/
H A Dlife.cc337 uint8_t *src0 = (cell_in_ + (y - 1) * cell_stride_);
338 uint8_t *src1 = src0 + cell_stride_;
353 u8x16_t src00 = *reinterpret_cast<u8x16_t*>(&src0[0]);
354 u8x16_t src01 = *reinterpret_cast<u8x16_t*>(&src0[16]);
428 src0 += 16;
434 src01 = *reinterpret_cast<u8x16_t*>(&src0[16]);
447 int count = src0[0] + src0[1] + src0[2] +
456 ++src0;
[all...]
/external/pixman/pixman/
H A Dpixman-arm-neon-asm-bilinear.S42 * All registers with single number (i.e. src0, tmp0) are 64-bits registers.
322 .macro bilinear_interleave src0, src1, dst0, dst1
323 vuzp.8 src0, src1
325 vuzp.8 src0, src1
330 numpix, src0, src1, src01, dst0, dst1, dst01
334 numpix, src0, src1, src01, dst0, dst1, dst01
336 bilinear_interleave src0, src1, dst0, dst1
340 numpix, src0, src1, src01, dst0, dst1, dst01
344 numpix, src0, src1, src01, dst0, dst1, dst01
346 bilinear_interleave src0, src
[all...]
/external/opencv/cv/src/
H A Dcvsegmentation.cpp351 CvMat sstub0, *src0; local
354 CV_CALL( src0 = cvGetMat( srcarr, &sstub0 ));
357 if( CV_MAT_TYPE(src0->type) != CV_8UC3 )
360 if( !CV_ARE_TYPES_EQ( src0, dst0 ))
363 if( !CV_ARE_SIZES_EQ( src0, dst0 ))
381 src_pyramid[0] = src0;
393 CV_CALL( mask0 = cvCreateMat( src0->rows, src0->cols, CV_8UC1 ));
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/
H A Dtgsi_ureg.h674 struct ureg_src src0, \
690 ureg_emit_src( ureg, src0 ); \
699 struct ureg_src src0, \
717 ureg_emit_src( ureg, src0 ); \
725 struct ureg_src src0, \
742 ureg_emit_src( ureg, src0 ); \
752 struct ureg_src src0, \
772 ureg_emit_src( ureg, src0 ); \
783 struct ureg_src src0, \
801 ureg_emit_src( ureg, src0 ); \
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