/external/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 125 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 473 unsigned Alignment, 477 if (Opcode == Instruction::Store && Src->isVectorTy() && Alignment != 16 && 472 getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace) const argument
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/external/llvm/lib/Target/ARM/ |
H A D | ARMConstantPoolValue.cpp | 64 unsigned Alignment) { 165 unsigned Alignment) { 166 return getExistingMachineCPValueImpl<ARMConstantPoolConstant>(CP, Alignment); 204 unsigned Alignment) { 205 return getExistingMachineCPValueImpl<ARMConstantPoolSymbol>(CP, Alignment); 244 unsigned Alignment) { 245 return getExistingMachineCPValueImpl<ARMConstantPoolMBB>(CP, Alignment); 63 getExistingMachineCPValue(MachineConstantPool *CP, unsigned Alignment) argument 164 getExistingMachineCPValue(MachineConstantPool *CP, unsigned Alignment) argument 203 getExistingMachineCPValue(MachineConstantPool *CP, unsigned Alignment) argument 243 getExistingMachineCPValue(MachineConstantPool *CP, unsigned Alignment) argument
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H A D | ARMConstantPoolValue.h | 71 unsigned Alignment) { 72 unsigned AlignMask = Alignment - 1; 109 unsigned Alignment) override; 168 unsigned Alignment) override; 202 unsigned Alignment) override; 238 unsigned Alignment) override; 70 getExistingMachineCPValueImpl(MachineConstantPool *CP, unsigned Alignment) argument
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H A D | ARMFastISel.cpp | 174 unsigned Alignment = 0, bool isZExt = true, 177 unsigned Alignment = 0); 182 unsigned Alignment); 959 unsigned Alignment, bool isZExt, bool allocReg) { 985 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) 1000 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) 1016 if (Alignment && Alignment < 958 ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment, bool isZExt, bool allocReg) argument 1081 ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr, unsigned Alignment) argument 2428 ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len, unsigned Alignment) argument 2530 unsigned Alignment = MTI.getAlignment(); local [all...] |
H A D | ARMISelDAGToDAG.cpp | 1002 unsigned Alignment = 0; local 1009 Alignment = MemSize; 1014 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment(); 1017 Align = CurDAG->getTargetConstant(Alignment, MVT::i32); 1657 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue(); local 1658 if (Alignment >= 32 && NumRegs == 4) 1659 Alignment = 32; 1660 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4)) 1661 Alignment = 16; 1662 else if (Alignment > 2072 unsigned Alignment = 0; local 2185 unsigned Alignment = 0; local [all...] |
H A D | ARMTargetTransformInfo.cpp | 134 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 575 unsigned ARMTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, argument 579 if (Src->isVectorTy() && Alignment != 16 &&
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 472 unsigned Alignment; // 0 = no alignment specified member in struct:__anon25988::ARMOperand::MemoryOp 620 /// getAlignmentLoc - Get the location of the Alignment token of this operand. 1082 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const { 1087 (alignOK || Memory.Alignment == Alignment); 1090 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1163 if (!isMem() || Memory.Alignment != 0) return false; 1185 if (!isMem() || Memory.Alignment != 0) return false; 1215 if (!isMem() || Memory.Alignment != 0) return false; 1226 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment ! 2674 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) argument [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonVarargsCallingConvention.h | 77 unsigned Alignment = local 88 Alignment = 8; 91 unsigned Offset3 = State.AllocateStack(Size, Alignment); 132 unsigned Alignment = local 137 unsigned Offset3 = State.AllocateStack(Size, Alignment);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 73 unsigned Alignment = 0); 75 unsigned Alignment = 0); 156 unsigned Alignment) { 215 unsigned Alignment) { 155 EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment) argument 214 EmitStore(MVT VT, unsigned SrcReg, Address &Addr, unsigned Alignment) argument
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H A D | MipsFrameLowering.h | 28 explicit MipsFrameLowering(const MipsSubtarget &sti, unsigned Alignment) argument 29 : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {}
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H A D | MipsISelLowering.cpp | 3586 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); local 3601 Alignment); 3630 MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, Alignment); 3651 Alignment = std::min(Alignment, LoadSizeInBytes); 3667 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 1564 unsigned Alignment = ST->getAlignment(); local 1570 isVolatile, Alignment); 2377 int64_t Alignment = cast<ConstantInt>(Align)->getZExtValue(); local 2378 Info.align = Alignment; 2406 int64_t Alignment = cast<ConstantInt>(Align)->getZExtValue(); local 2407 Info.align = Alignment;
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1416 unsigned Alignment; local 1420 Alignment = LD->getAlignment(); 1424 Alignment = ST->getAlignment(); 1462 if (Alignment < 4) 2214 // | | Alignment padding | 3261 /// by "Src" to address "Dst" of size "Size". Alignment information is
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H A D | PPCTargetTransformInfo.cpp | 107 unsigned Alignment, 382 unsigned PPCTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, argument 390 TargetTransformInfo::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace); 407 if (SrcBytes && Alignment && Alignment < SrcBytes && !UnalignedAltivec) { 408 Cost += LT.first*(SrcBytes/Alignment-1);
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 704 unsigned Alignment = TD->getPrefTypeAlignment(EltType); local 709 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZConstantPoolValue.cpp | 40 getExistingMachineCPValue(MachineConstantPool *CP, unsigned Alignment) { argument 41 unsigned AlignMask = Alignment - 1;
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H A D | SystemZConstantPoolValue.h | 44 unsigned Alignment) override;
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H A D | SystemZLongBranch.cpp | 85 unsigned Alignment; member in struct:__anon26159::MBBInfo 91 : Address(0), Size(0), Alignment(0), NumTerminators(0) {} 178 if (Block.Alignment > Position.KnownBits) { 181 Position.Address += ((uint64_t(1) << Block.Alignment) - 183 Position.KnownBits = Block.Alignment; 187 uint64_t AlignMask = (uint64_t(1) << Block.Alignment) - 1; 277 Block.Alignment = MBB->getAlignment();
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/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 944 unsigned Alignment = S->getAlignment(); local 946 if (Alignment == 0) // Ensure that codegen never sees alignment 0 947 Alignment = ABIAlignment; 948 bool Aligned = Alignment >= ABIAlignment; 3250 // Alignment of vector types. FIXME! 3350 unsigned Alignment = LI->getAlignment(); local 3352 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3353 Alignment = DL.getABITypeAlignment(LI->getType()); 3359 XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment);
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H A D | X86ISelLowering.cpp | 5849 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); local 5852 false, false, false, Alignment); 11135 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 11138 false, false, false, Alignment); 11214 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 11217 false, false, false, Alignment); 11390 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 11393 false, false, false, Alignment); 11425 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 11428 false, false, false, Alignment); [all...] |
H A D | X86InstrInfo.cpp | 3289 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); local 3291 (MF.getTarget().getFrameLowering()->getStackAlignment() >= Alignment) || 3306 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); local 3308 (*MMOBegin)->getAlignment() >= Alignment; 3326 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); local 3328 (MF.getTarget().getFrameLowering()->getStackAlignment() >= Alignment) || 3341 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); local 3343 (*MMOBegin)->getAlignment() >= Alignment; 4349 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); local 4353 Alignment 4401 unsigned Alignment = 0; local 4753 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; local 4796 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; local [all...] |
H A D | X86InstrInfo.h | 407 unsigned Size, unsigned Alignment) const;
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H A D | X86JITInfo.cpp | 452 const unsigned Alignment = 8; local 458 const unsigned Alignment = 4; 463 return JCE.allocIndirectGV(GV, Buffer, sizeof(Buffer), Alignment);
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H A D | X86TargetTransformInfo.cpp | 96 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 778 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, argument 799 Alignment,
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1818 unsigned Alignment = ST->getAlignment(); local 1819 if (Alignment >= ABIAlignment) { 1825 LD->getAlignment() == Alignment && 1831 Alignment, false, ST->getPointerInfo(),
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