/external/llvm/lib/CodeGen/ |
H A D | CalcSpillWeights.cpp | 43 // Return the preferred allocation register for reg, given a COPY instruction. 44 static unsigned copyHint(const MachineInstr *mi, unsigned reg, argument 48 if (mi->getOperand(0).getReg() == reg) { 64 const TargetRegisterClass *rc = mri.getRegClass(reg); 70 // reg:sub should match the physreg hreg. 110 bool noHint = mri.getRegAllocationHint(li.reg).first != 0; 116 I = mri.reg_instr_begin(li.reg), E = mri.reg_instr_end(); 135 std::tie(reads, writes) = mi->readsWritesVirtualRegister(li.reg); 149 unsigned hint = copyHint(mi, li.reg, tri, mri); 170 mri.setRegAllocationHint(li.reg, [all...] |
/external/ltrace/sysdeps/linux-gnu/arm/ |
H A D | regs.h | 38 int arm_get_register(struct process *proc, enum arm_register reg, uint32_t *lp); 41 int arm_get_register_offpc(struct process *proc, enum arm_register reg,
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/external/lldb/source/Plugins/Process/Utility/ |
H A D | RegisterContextDarwin_x86_64.cpp | 238 #define GPR_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_x86_64::GPR, reg)) 239 #define FPU_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_x86_64::FPU, reg) + sizeof (RegisterContextDarwin_x86_64::GPR)) 240 #define EXC_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_x86_64::EXC, reg) + sizeof (RegisterContextDarwin_x86_64::GPR) + sizeof (RegisterContextDarwin_x86_64::FPU)) 246 #define DEFINE_GPR(reg, alt) #reg, alt, sizeof(((RegisterContextDarwin_x86_64::GPR *)NULL)->reg), GPR_OFFSET(reg), eEncodingUin 339 GetRegisterInfoAtIndex(size_t reg) argument 493 uint32_t reg = gpr_rax + i; local 606 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; local 733 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; local 905 ConvertRegisterKindToRegisterNumber(uint32_t kind, uint32_t reg) argument [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/ |
H A D | tgsi_scan.c | 148 uint reg; local 149 for (reg = fulldecl->Range.First; 150 reg <= fulldecl->Range.Last; 151 reg++) { 154 info->file_mask[file] |= (1 << reg); 156 info->file_max[file] = MAX2(info->file_max[file], (int)reg); 159 info->input_semantic_name[reg] = (ubyte)fulldecl->Semantic.Name; 160 info->input_semantic_index[reg] = (ubyte)fulldecl->Semantic.Index; 161 info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate; 162 info->input_centroid[reg] 218 uint reg = info->immediate_count++; local [all...] |
/external/libunwind/src/hppa/ |
H A D | Gget_save_loc.c | 29 unw_get_save_loc (unw_cursor_t *cursor, int reg, unw_save_loc_t *sloc) argument
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H A D | unwind_i.h | 44 extern dwarf_loc_t hppa_scratch_loc (struct cursor *c, unw_regnum_t reg);
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/external/libunwind/src/ppc64/ |
H A D | unwind_i.h | 49 extern dwarf_loc_t ppc64_scratch_loc (struct cursor *c, unw_regnum_t reg);
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H A D | regname.c | 158 unw_regname (unw_regnum_t reg) argument 160 if (reg < (unw_regnum_t) ARRAY_SIZE (regname)) 161 return regname[reg];
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/external/llvm/lib/Target/R600/ |
H A D | R600Defines.h | 59 #define GET_REG_CHAN(reg) ((reg) >> HW_CHAN_SHIFT) 60 #define GET_REG_INDEX(reg) ((reg) & HW_REG_MASK)
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H A D | R600RegisterInfo.h | 32 unsigned getHWRegChan(unsigned reg) const;
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/external/mesa3d/src/gallium/auxiliary/tgsi/ |
H A D | tgsi_scan.c | 148 uint reg; local 149 for (reg = fulldecl->Range.First; 150 reg <= fulldecl->Range.Last; 151 reg++) { 154 info->file_mask[file] |= (1 << reg); 156 info->file_max[file] = MAX2(info->file_max[file], (int)reg); 159 info->input_semantic_name[reg] = (ubyte)fulldecl->Semantic.Name; 160 info->input_semantic_index[reg] = (ubyte)fulldecl->Semantic.Index; 161 info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate; 162 info->input_centroid[reg] 218 uint reg = info->immediate_count++; local [all...] |
/external/chromium_org/v8/src/arm/ |
H A D | disasm-arm.cc | 75 void PrintRegister(int reg); 76 void PrintSRegister(int reg); 77 void PrintDRegister(int reg); 164 void Decoder::PrintRegister(int reg) { argument 165 Print(converter_.NameOfCPURegister(reg)); 170 void Decoder::PrintSRegister(int reg) { argument 171 Print(VFPRegisters::Name(reg, false)); 176 void Decoder::PrintDRegister(int reg) { argument 177 Print(VFPRegisters::Name(reg, true)); 304 int reg local 308 int reg = instr->RdValue(); local 312 int reg = instr->RsValue(); local 316 int reg = instr->RmValue(); local 320 int reg = instr->RtValue(); local 327 int reg = 0; local 357 int reg = -1; local [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
H A D | brw_fs.cpp | 171 fs_inst::overwrites_reg(const fs_reg ®) argument 173 return (reg.file == dst.file && 174 reg.reg == dst.reg && 175 reg.reg_offset >= dst.reg_offset && 176 reg.reg_offset < dst.reg_offset + regs_written()); 259 reg == r.reg && 440 /** Fixed HW reg constructo 441 fs_reg(enum register_file file, int reg) argument 450 fs_reg(enum register_file file, int reg, uint32_t type) argument 481 const fs_reg *reg = (const fs_reg *)data; local 600 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); local 671 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); local 763 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); local 1077 int reg = virtual_grf_alloc(1); local 1936 get_instruction_generating_reg(fs_inst *start, fs_inst *end, fs_reg reg) argument [all...] |
H A D | brw_fs_schedule_instructions.cpp | 280 add_dep(last_grf_write[inst->src[i].reg], n); 308 add_dep(last_grf_write[inst->dst.reg], n); 309 last_grf_write[inst->dst.reg] = n; 311 int reg = inst->dst.reg & ~BRW_MRF_COMPR4; local 313 add_dep(last_mrf_write[reg], n); 314 last_mrf_write[reg] = n; 316 if (inst->dst.reg & BRW_MRF_COMPR4) 317 reg += 4; 319 reg 395 int reg = inst->dst.reg & ~BRW_MRF_COMPR4; local [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_fs.cpp | 171 fs_inst::overwrites_reg(const fs_reg ®) argument 173 return (reg.file == dst.file && 174 reg.reg == dst.reg && 175 reg.reg_offset >= dst.reg_offset && 176 reg.reg_offset < dst.reg_offset + regs_written()); 259 reg == r.reg && 440 /** Fixed HW reg constructo 441 fs_reg(enum register_file file, int reg) argument 450 fs_reg(enum register_file file, int reg, uint32_t type) argument 481 const fs_reg *reg = (const fs_reg *)data; local 600 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); local 671 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); local 763 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); local 1077 int reg = virtual_grf_alloc(1); local 1936 get_instruction_generating_reg(fs_inst *start, fs_inst *end, fs_reg reg) argument [all...] |
H A D | brw_fs_schedule_instructions.cpp | 280 add_dep(last_grf_write[inst->src[i].reg], n); 308 add_dep(last_grf_write[inst->dst.reg], n); 309 last_grf_write[inst->dst.reg] = n; 311 int reg = inst->dst.reg & ~BRW_MRF_COMPR4; local 313 add_dep(last_mrf_write[reg], n); 314 last_mrf_write[reg] = n; 316 if (inst->dst.reg & BRW_MRF_COMPR4) 317 reg += 4; 319 reg 395 int reg = inst->dst.reg & ~BRW_MRF_COMPR4; local [all...] |
/external/chromium_org/v8/src/ia32/ |
H A D | debug-ia32.cc | 94 Register reg = { r }; local 96 __ push(reg); 100 __ test(reg, Immediate(0xc0000000)); 103 __ SmiTag(reg); 104 __ push(reg); 125 Register reg = { r }; local 127 __ Move(reg, Immediate(kDebugZapValue)); 129 bool taken = reg.code() == esi.code(); 131 __ pop(reg); 135 __ pop(reg); [all...] |
/external/chromium_org/v8/src/x87/ |
H A D | debug-x87.cc | 94 Register reg = { r }; local 96 __ push(reg); 100 __ test(reg, Immediate(0xc0000000)); 103 __ SmiTag(reg); 104 __ push(reg); 125 Register reg = { r }; local 127 __ Move(reg, Immediate(kDebugZapValue)); 129 bool taken = reg.code() == esi.code(); 131 __ pop(reg); 135 __ pop(reg); [all...] |
/external/libunwind/src/aarch64/ |
H A D | Gget_save_loc.c | 30 unw_get_save_loc (unw_cursor_t *cursor, int reg, unw_save_loc_t *sloc) argument 35 switch (reg) 71 loc = c->dwarf.loc[reg];
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/external/libunwind/src/mips/ |
H A D | Gget_save_loc.c | 30 unw_get_save_loc (unw_cursor_t *cursor, int reg, unw_save_loc_t *sloc) argument 37 switch (reg) 72 loc = c->dwarf.loc[reg - UNW_MIPS_R0];
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/external/libunwind/src/x86_64/ |
H A D | Ginit.c | 209 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, argument 215 if (unw_is_fpreg (reg)) 218 if (!(addr = x86_64_r_uc_addr (uc, reg))) 224 Debug (12, "%s <- 0x%016lx\n", unw_regname (reg), *val); 229 Debug (12, "%s -> 0x%016lx\n", unw_regname (reg), *val); 234 Debug (1, "bad register number %u\n", reg); 239 access_fpreg (unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, argument 245 if (!unw_is_fpreg (reg)) 248 if (!(addr = x86_64_r_uc_addr (uc, reg))) 253 Debug (12, "%s <- %08lx.%08lx.%08lx\n", unw_regname (reg), [all...] |
/external/valgrind/main/coregrind/m_debuginfo/ |
H A D | readdwarf.c | 1992 reg # for Reg 2036 /* The CFA entry. This can be either reg+/-offset or an expr. */ 2037 Bool cfa_is_regoff; /* True=>is reg+offset; False=>is expr */ 2042 RegRule reg[N_CFI_REGS]; member in struct:__anon32467::UnwindContextState 2047 /* array of CfiExpr, shared by reg[] and cfa_expr_ix */ 2069 ppRegRule(ctx->exprs, &ctxs->reg[i]); 2093 ctx->state[j].reg[i].tag = RR_Undef; 2094 /* ctx->state[j].reg[i].arg = 0; */ 2099 ctx->state[j].reg[11].tag = RR_Same; 2100 /* ctx->state[j].reg[1 2788 Int ix, ix2, reg; local 3026 Int off, reg, reg2, len, j; local 3433 Int off, coff, reg, reg2, len; local [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/svga/ |
H A D | svga_tgsi_decl_sm30.c | 95 * For example, if usage = SVGA3D_DECLUSAGE_TEXCOORD, reg.num = 1, and 100 SVGA3dShaderDestToken reg, 115 dcl.dst = reg; 132 SVGA3dShaderDestToken reg = local 135 if (!emit_decl( emit, reg, 0, 0 )) 152 struct src_register reg; local 162 reg = src_register( SVGA3DREG_INPUT, 165 *out = emit->ps_depth_fog = reg; 169 return emit_decl( emit, dst( reg ), SVGA3D_DECLUSAGE_TEXCOORD, 0 ); 183 SVGA3dShaderDestToken reg; local 99 emit_decl(struct svga_shader_emitter *emit, SVGA3dShaderDestToken reg, unsigned usage, unsigned index) argument 402 SVGA3dShaderDestToken reg; local [all...] |
/external/mesa3d/src/gallium/drivers/svga/ |
H A D | svga_tgsi_decl_sm30.c | 95 * For example, if usage = SVGA3D_DECLUSAGE_TEXCOORD, reg.num = 1, and 100 SVGA3dShaderDestToken reg, 115 dcl.dst = reg; 132 SVGA3dShaderDestToken reg = local 135 if (!emit_decl( emit, reg, 0, 0 )) 152 struct src_register reg; local 162 reg = src_register( SVGA3DREG_INPUT, 165 *out = emit->ps_depth_fog = reg; 169 return emit_decl( emit, dst( reg ), SVGA3D_DECLUSAGE_TEXCOORD, 0 ); 183 SVGA3dShaderDestToken reg; local 99 emit_decl(struct svga_shader_emitter *emit, SVGA3dShaderDestToken reg, unsigned usage, unsigned index) argument 402 SVGA3dShaderDestToken reg; local [all...] |
/external/pcre/dist/sljit/ |
H A D | sljitNativePPC_64.c | 41 #define PUSH_RLDICR(reg, shift) \ 42 push_inst(compiler, RLDI(reg, reg, 63 - shift, shift, 1)) 44 static sljit_si load_immediate(struct sljit_compiler *compiler, sljit_si reg, sljit_sw imm) argument 52 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); 55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); 58 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); 59 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; 70 FAIL_IF(push_inst(compiler, ADDI | D(reg) | 392 emit_const(struct sljit_compiler *compiler, sljit_si reg, sljit_sw init_value) argument [all...] |