| /external/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.h | 119 MachineRegisterInfo &MRI; member in class:llvm::AggressiveAntiDepBreaker
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| H A D | OptimizePHIs.cpp | 32 MachineRegisterInfo *MRI; member in class:__anon25781::OptimizePHIs
68 MRI = &Fn.getRegInfo();
106 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
113 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
146 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) {
170 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
173 MRI->replaceRegWith(OldReg, SingleValReg);
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| H A D | ProcessImplicitDefs.cpp | 30 MachineRegisterInfo *MRI; member in class:__anon25785::ProcessImplicitDefs
83 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
143 MRI = &MF.getRegInfo();
144 assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
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| H A D | UnreachableBlockElim.cpp | 196 MachineRegisterInfo &MRI = F.getRegInfo(); local
197 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
198 MRI.replaceRegWith(Output, Input);
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| H A D | CalcSpillWeights.cpp | 33 MachineRegisterInfo &MRI = MF.getRegInfo(); local
35 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
37 if (MRI.reg_nodbg_empty(Reg))
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| H A D | LLVMTargetMachine.cpp | 169 const MCRegisterInfo &MRI = *getRegisterInfo(); local
178 MII, MRI, STI);
183 MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context);
185 MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
197 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI,
199 MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
268 const MCRegisterInfo &MRI = *getRegisterInfo(); local
270 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI,
272 MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
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| H A D | LiveRangeCalc.h | 38 const MachineRegisterInfo *MRI; member in class:llvm::LiveRangeCalc
128 LiveRangeCalc() : MF(nullptr), MRI(nullptr), Indexes(nullptr),
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| H A D | MachineCopyPropagation.cpp | 38 MachineRegisterInfo *MRI; member in class:__anon25763::MachineCopyPropagation
162 if (!MRI->isReserved(Def) &&
163 (!MRI->isReserved(Src) || NoInterveningSideEffect(CopyMI, MI)) &&
282 if (MRI->isReserved(Reg) || !MaskMO.clobbersPhysReg(Reg))
321 if (!MRI->isReserved((*DI)->getOperand(0).getReg())) {
340 MRI = &MF.getRegInfo();
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 32 const MachineRegisterInfo *MRI; member in class:__anon25948::AArch64StorePairSuppress
123 MRI = &MF->getRegInfo();
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| /external/llvm/lib/Target/MSP430/MCTargetDesc/ |
| H A D | MSP430MCTargetDesc.cpp | 65 const MCRegisterInfo &MRI,
68 return new MSP430InstPrinter(MAI, MII, MRI);
61 createMSP430MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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| /external/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| H A D | NVPTXMCTargetDesc.cpp | 65 const MCRegisterInfo &MRI,
68 return new NVPTXInstPrinter(MAI, MII, MRI, STI);
61 createNVPTXMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXReplaceImageHandles.cpp | 316 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
319 MachineInstr *MI = MRI.getVRegDef(Op.getReg());
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCAsmBackend.cpp | 211 const MCRegisterInfo &MRI,
210 createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
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| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZMCAsmBackend.cpp | 113 const MCRegisterInfo &MRI,
112 createSystemZMCAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo(); local
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]);
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg);
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
123 MachineRegisterInfo & MRI,
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
134 MRI
122 AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI, unsigned physReg, unsigned virtReg) argument
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| H A D | AMDGPUMCTargetDesc.cpp | 68 const MCRegisterInfo &MRI,
70 return new AMDGPUInstPrinter(MAI, MII, MRI);
64 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 53 MachineRegisterInfo &MRI; member in class:llvm::FastISel
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| H A D | LiveVariables.h | 111 MachineRegisterInfo &MRI);
130 MachineRegisterInfo* MRI; member in class:llvm::LiveVariables
282 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
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| H A D | RegisterScavenging.h | 34 MachineRegisterInfo* MRI; member in class:llvm::RegScavenger
165 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
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| H A D | VirtRegMap.h | 41 MachineRegisterInfo *MRI; member in class:llvm::VirtRegMap
85 MachineRegisterInfo &getRegInfo() const { return *MRI; }
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| /external/llvm/include/llvm/MC/ |
| H A D | MCInstPrinter.h | 41 const MCRegisterInfo &MRI; member in class:llvm::MCInstPrinter
60 : CommentStream(nullptr), MAI(mai), MII(mii), MRI(mri),
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 60 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, argument
73 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
116 const MCRegisterInfo &MRI,
119 return new AArch64InstPrinter(MAI, MII, MRI, STI);
121 return new AArch64AppleInstPrinter(MAI, MII, MRI, STI);
112 createAArch64MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| H A D | ARMInstPrinter.cpp | 63 const MCRegisterInfo &MRI,
65 MCInstPrinter(MAI, MII, MRI) {
273 const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
283 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
284 &MRI.getRegClass(ARM::GPRPairRegClassID)));
772 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
774 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
1321 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1322 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1334 unsigned Reg0 = MRI
61 ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 154 MachineRegisterInfo *MRI = &MF.getRegInfo(); local
155 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
195 MachineRegisterInfo *MRI = &MF.getRegInfo(); local
196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 223 const MCRegisterInfo &MRI,
226 return(new HexagonInstPrinter(MAI, MII, MRI));
219 createHexagonMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
|