Searched refs:Dst (Results 51 - 75 of 197) sorted by relevance

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/external/llvm/lib/Target/R600/MCTargetDesc/
H A DAMDGPUAsmBackend.cpp76 uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset()); local
78 *Dst = (Value - 4) / 4;
/external/llvm/lib/Target/R600/
H A DSILowerControlFlow.cpp200 unsigned Dst = MI.getOperand(0).getReg(); local
204 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
209 .addReg(Dst);
220 unsigned Dst = MI.getOperand(0).getReg(); local
223 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
234 unsigned Dst = MI.getOperand(0).getReg(); local
238 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
249 unsigned Dst = MI.getOperand(0).getReg(); local
253 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
404 unsigned Dst local
425 unsigned Dst = MI.getOperand(0).getReg(); local
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/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/
H A Dtgsi_exec.c585 uint writemask = inst->Dst[0].Register.WriteMask;
598 inst->Dst[0].Register.File) &&
600 inst->Dst[0].Register.Index) ||
602 inst->Dst[0].Register.Indirect)) {
606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1908 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1909 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1987 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1988 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2059 if (inst->Dst[
[all...]
/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_exec.c585 uint writemask = inst->Dst[0].Register.WriteMask;
598 inst->Dst[0].Register.File) &&
600 inst->Dst[0].Register.Index) ||
602 inst->Dst[0].Register.Indirect)) {
606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1908 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1909 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1987 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1988 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2059 if (inst->Dst[
[all...]
/external/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp234 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
236 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
240 /// The Src and Dst ranges may overlap.
241 void MachineRegisterInfo::moveOperands(MachineOperand *Dst, argument
244 assert(Src != Dst && NumOps && "Noop moveOperands");
246 // Copy backwards if Dst is within the Src range.
248 if (Dst >= Src && Dst < Src + NumOps) {
250 Dst += NumOps - 1;
256 new (Dst) MachineOperan
[all...]
H A DRegisterCoalescer.cpp217 unsigned &Src, unsigned &Dst,
220 Dst = MI->getOperand(0).getReg();
225 Dst = MI->getOperand(0).getReg();
257 unsigned Src, Dst, SrcSub, DstSub; local
258 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
262 // If one register is a physreg, it must be Dst.
264 if (TargetRegisterInfo::isPhysicalRegister(Dst))
266 std::swap(Src, Dst);
273 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
276 Dst
216 isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI, unsigned &Src, unsigned &Dst, unsigned &SrcSub, unsigned &DstSub) argument
351 unsigned Src, Dst, SrcSub, DstSub; local
[all...]
H A DBasicTargetTransformInfo.cpp108 unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
358 unsigned BasicTTI::getCastInstrCost(unsigned Opcode, Type *Dst, argument
365 std::pair<unsigned, MVT> DstLT = TLI->getTypeLegalizationCost(Dst);
390 if (!Src->isVectorTy() && !Dst->isVectorTy()) {
405 if (Dst->isVectorTy() && Src->isVectorTy()) {
428 unsigned Num = Dst->getVectorNumElements();
429 unsigned Cost = TopTTI->getCastInstrCost(Opcode, Dst->getScalarType(),
434 return getScalarizationOverhead(Dst, true, true) + Num * Cost;
443 (Dst->isVectorTy()? getScalarizationOverhead(Dst, tru
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/external/clang/lib/StaticAnalyzer/Core/
H A DCheckerManager.cpp95 ExplodedNodeSet &Dst,
104 Dst.insert(Src);
114 CurrSet = &Dst;
167 ExplodedNodeSet &Dst,
174 expandGraphWithCheckers(C, Dst, Src);
206 ExplodedNodeSet &Dst,
215 expandGraphWithCheckers(C, Dst, Src);
249 ExplodedNodeSet &Dst,
258 expandGraphWithCheckers(C, Dst, Src);
297 void CheckerManager::runCheckersForLocation(ExplodedNodeSet &Dst, argument
94 expandGraphWithCheckers(CHECK_CTX checkCtx, ExplodedNodeSet &Dst, const ExplodedNodeSet &Src) argument
166 runCheckersForStmt(bool isPreVisit, ExplodedNodeSet &Dst, const ExplodedNodeSet &Src, const Stmt *S, ExprEngine &Eng, bool WasInlined) argument
205 runCheckersForObjCMessage(bool isPreVisit, ExplodedNodeSet &Dst, const ExplodedNodeSet &Src, const ObjCMethodCall &msg, ExprEngine &Eng, bool WasInlined) argument
248 runCheckersForCallEvent(bool isPreVisit, ExplodedNodeSet &Dst, const ExplodedNodeSet &Src, const CallEvent &Call, ExprEngine &Eng, bool WasInlined) argument
337 runCheckersForBind(ExplodedNodeSet &Dst, const ExplodedNodeSet &Src, SVal location, SVal val, const Stmt *S, ExprEngine &Eng, const ProgramPoint &PP) argument
356 runCheckersForEndFunction(NodeBuilderContext &BC, ExplodedNodeSet &Dst, ExplodedNode *Pred, ExprEngine &Eng) argument
401 runCheckersForBranchCondition(const Stmt *Condition, ExplodedNodeSet &Dst, ExplodedNode *Pred, ExprEngine &Eng) argument
450 runCheckersForDeadSymbols(ExplodedNodeSet &Dst, const ExplodedNodeSet &Src, SymbolReaper &SymReaper, const Stmt *S, ExprEngine &Eng, ProgramPoint::Kind K) argument
524 runCheckersForEvalCall(ExplodedNodeSet &Dst, const ExplodedNodeSet &Src, const CallEvent &Call, ExprEngine &Eng) argument
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/tests/
H A Drc_test_helpers.c287 DBG("Dst Reg File=%u Index=%d Writemask=%d\n",
299 struct match_info Dst; member in struct:inst_tokens
353 tokens.Dst.String = inst_str + matches[3].rm_so;
354 tokens.Dst.Length = match_length(matches, 3);
357 dst_str = malloc(sizeof(char) * (tokens.Dst.Length + 1));
358 strncpy(dst_str, tokens.Dst.String, tokens.Dst.Length);
359 dst_str[tokens.Dst.Length] = '\0';
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/
H A Dr300_vs_draw.c251 new_inst.Dst[0].Register.File = TGSI_FILE_OUTPUT;
252 new_inst.Dst[0].Register.Index = vsctx->pos_output;
253 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
263 new_inst.Dst[0].Register.File = TGSI_FILE_OUTPUT;
264 new_inst.Dst[0].Register.Index = vsctx->num_outputs - 1;
265 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
276 struct tgsi_full_dst_register *dst = &inst->Dst[i];
/external/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp229 unsigned Dst = MI->getOperand(0).getReg(); local
232 Use = MRI->use_instr_nodbg_begin(Dst),
265 unsigned Dst, unsigned Src, bool IsKill) {
268 Dst)
333 unsigned Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass); local
338 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst)
345 insertCopy(TII, MI, MI->getOperand(0).getReg(), Dst, true);
264 insertCopy(const AArch64InstrInfo *TII, MachineInstr *MI, unsigned Dst, unsigned Src, bool IsKill) argument
/external/mesa3d/src/gallium/drivers/r300/compiler/tests/
H A Drc_test_helpers.c287 DBG("Dst Reg File=%u Index=%d Writemask=%d\n",
299 struct match_info Dst; member in struct:inst_tokens
353 tokens.Dst.String = inst_str + matches[3].rm_so;
354 tokens.Dst.Length = match_length(matches, 3);
357 dst_str = malloc(sizeof(char) * (tokens.Dst.Length + 1));
358 strncpy(dst_str, tokens.Dst.String, tokens.Dst.Length);
359 dst_str[tokens.Dst.Length] = '\0';
/external/mesa3d/src/gallium/drivers/r300/
H A Dr300_vs_draw.c251 new_inst.Dst[0].Register.File = TGSI_FILE_OUTPUT;
252 new_inst.Dst[0].Register.Index = vsctx->pos_output;
253 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
263 new_inst.Dst[0].Register.File = TGSI_FILE_OUTPUT;
264 new_inst.Dst[0].Register.Index = vsctx->num_outputs - 1;
265 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
276 struct tgsi_full_dst_register *dst = &inst->Dst[i];
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
H A Dradeon_variable.c60 if (var_ptr->Dst.WriteMask == RC_MASK_W) {
265 assert(var->Dst.Index == friend->Dst.Index);
283 new->Dst.File = DstFile;
284 new->Dst.Index = DstIndex;
285 new->Dst.WriteMask = DstWriteMask;
394 writemask |= var->Dst.WriteMask;
525 var->Inst->IP, var->Dst.Index, var->Dst.WriteMask);
/external/llvm/include/llvm/Support/
H A DGCOV.h253 GCOVEdge(GCOVBlock &S, GCOVBlock &D) : Src(S), Dst(D), Count(0) {}
256 GCOVBlock &Dst; member in struct:llvm::GCOVEdge
294 EdgeWeight(GCOVBlock *D): Dst(D), Count(0) {}
296 GCOVBlock *Dst; member in struct:llvm::GCOVBlock::EdgeWeight
302 return E1->Dst.Number < E2->Dst.Number;
318 assert(&Edge->Dst == this); // up to caller to ensure edge is valid
324 if (DstEdges.size() && DstEdges.back()->Dst.Number > Edge->Dst.Number)
/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_variable.c60 if (var_ptr->Dst.WriteMask == RC_MASK_W) {
265 assert(var->Dst.Index == friend->Dst.Index);
283 new->Dst.File = DstFile;
284 new->Dst.Index = DstIndex;
285 new->Dst.WriteMask = DstWriteMask;
394 writemask |= var->Dst.WriteMask;
525 var->Inst->IP, var->Dst.Index, var->Dst.WriteMask);
/external/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp30 SDValue Dst, SDValue Src,
81 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
133 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
149 SDValue Chain, SDValue Dst,
166 Entry.Node = Dst;
28 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
148 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
/external/llvm/include/llvm/Transforms/Utils/
H A DBuildLibCalls.h52 Value *EmitStrCpy(Value *Dst, Value *Src, IRBuilder<> &B,
58 Value *EmitStrNCpy(Value *Dst, Value *Src, Value *Len, IRBuilder<> &B,
63 /// This expects that the Len and ObjSize have type 'intptr_t' and Dst/Src
65 Value *EmitMemCpyChk(Value *Dst, Value *Src, Value *Len, Value *ObjSize,
H A DBasicBlockUtils.h116 /// SplitCriticalEdge - If an edge from Src to Dst is critical, split the edge
120 inline BasicBlock *SplitCriticalEdge(BasicBlock *Src, BasicBlock *Dst, argument
128 if (TI->getSuccessor(i) == Dst)
/external/llvm/lib/Analysis/
H A DBranchProbabilityInfo.cpp555 isEdgeHot(const BasicBlock *Src, const BasicBlock *Dst) const {
558 return getEdgeProbability(Src, Dst) > BranchProbability(4, 5);
602 succ_const_iterator Dst) const {
603 return getEdgeWeight(Src, Dst.getSuccessorIndex());
607 /// of all raw edge weights from Src to Dst.
609 getEdgeWeight(const BasicBlock *Src, const BasicBlock *Dst) const {
613 if (*I == Dst) {
641 /// Get the probability of going from Src to Dst. It returns the sum of all
642 /// probabilities for edges from Src to Dst.
644 getEdgeProbability(const BasicBlock *Src, const BasicBlock *Dst) cons
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/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/util/
H A Du_linkage.c85 if(finst->Dst[i].Register.File == file)
87 unsigned idx = finst->Dst[i].Register.Index;
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DSubEngine.h71 ExplodedNodeSet &Dst,
80 ExplodedNodeSet &Dst,
/external/elfutils/0.153/libelf/
H A Dcommon.h168 #define CONVERT_TO(Dst, Var) \
169 (Dst) = (sizeof (Var) == 1 \
/external/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.h29 SDValue Dst, SDValue Src,
36 SDValue Chain, SDValue Dst, SDValue Byte,
/external/mesa3d/src/gallium/auxiliary/util/
H A Du_linkage.c85 if(finst->Dst[i].Register.File == file)
87 unsigned idx = finst->Dst[i].Register.Index;

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