/external/kernel-headers/original/uapi/asm-x86/asm/ |
H A D | ptrace-abi.h | 39 #define RAX 80 macro
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/external/llvm/test/MC/X86/ |
H A D | intel-syntax-encoding.s | 25 mov QWORD PTR [RSP - 16], RAX
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H A D | intel-syntax.s | 19 mov RAX, QWORD PTR [RSP] 25 mov EAX, DWORD PTR [RSP + 4*RAX - 24] 65 mov RAX, QWORD PTR FS:[320] 67 mov RAX, QWORD PTR FS:320 69 mov QWORD PTR FS:320, RAX 71 mov QWORD PTR FS:20[rbx], RAX 380 shld [RAX], BX 381 shld [RAX], BX, CL 385 shrd [RAX], BX 386 shrd [RAX], B [all...] |
/external/libunwind/src/x86_64/ |
H A D | unwind_i.h | 39 #define RAX 0 macro
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H A D | init.h | 49 c->dwarf.loc[RAX] = REG_INIT_LOC(c, rax, RAX);
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H A D | Gregs.c | 104 loc = c->dwarf.loc[(reg == UNW_X86_64_RAX) ? RAX : RDX];
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H A D | Gos-freebsd.c | 111 c->dwarf.loc[RAX] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RAX, 0);
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/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmInstrumentation.cpp | 357 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX)); 369 Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI)); 370 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX) 371 .addReg(X86::RAX).addImm(3)); 378 X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc())); 430 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX)); 438 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX)); 444 Inst.addOperand(MCOperand::CreateReg(X86::RAX)); 448 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX) 449 .addReg(X86::RAX) [all...] |
H A D | X86Operand.h | 343 case X86::RAX: return X86::EAX;
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H A D | X86AsmParser.cpp | 2196 return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
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/external/lzma/Asm/x86/ |
H A D | 7zAsm.asm | 62 r0 equ RAX
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/external/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 250 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 277 if (Op0 == X86::RAX && Op1 == X86::EAX) 311 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 693 BaseReg = X86::RAX; ScaleVal = 1; 701 IndexReg = X86::RAX; break; 703 IndexReg = X86::RAX; break; 706 IndexReg = X86::RAX; break; 708 IndexReg = X86::RAX; break; 710 IndexReg = X86::RAX; SegmentReg = X86::CS; break; 888 .addReg(X86::RAX)); [all...] |
H A D | X86RegisterInfo.cpp | 550 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 562 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 599 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 635 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 671 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 672 return X86::RAX;
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H A D | X86SelectionDAGInfo.cpp | 106 ValReg = X86::RAX;
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H A D | X86FrameLowering.cpp | 104 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI, 171 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) 697 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) 721 .addReg(X86::RAX) 1352 // The MOV R10, RAX needs to be in a different block, since the RET we emit in 1472 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
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H A D | X86FastISel.cpp | 1073 unsigned RetReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 1620 { &X86::GR64RegClass, X86::RAX, X86::RDX, { 1621 { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv 1623 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv 2438 static const unsigned Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX }; 2439 // First copy the first operand into RAX, which is an implicit input to
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H A D | X86ISelDAGToDAG.cpp | 2225 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break; 2285 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX; 2431 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
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H A D | X86ISelLowering.cpp | 620 setExceptionPointerRegister(X86::RAX); 1933 // which is returned in RAX / RDX. 1969 X86::RAX : X86::EAX; 1973 // RAX/EAX now acts like a return value. 10379 X86::RAX, X86II::MO_TLSGD); 10395 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX, 10542 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 13196 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 14287 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1)); 14328 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MV [all...] |
H A D | X86InstrInfo.cpp | 5529 // Insert a Copy from TLSBaseAddrReg to RAX/EAX. 5532 is64Bit ? X86::RAX : X86::EAX) 5556 // Insert a copy from RAX/EAX to TLSBaseAddrReg. 5561 .addReg(is64Bit ? X86::RAX : X86::EAX);
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/external/llvm/lib/Target/X86/Disassembler/ |
H A D | X86DisassemblerDecoder.h | 171 ENTRY(RAX) \ 189 ENTRY(RAX) \
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/external/valgrind/main/VEX/auxprogs/ |
H A D | genoffsets.c | 103 GENOFFSET(AMD64,amd64,RAX);
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/external/valgrind/main/coregrind/m_sigframe/ |
H A D | sigframe-amd64-linux.c | 358 SC2(rax,RAX);
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/external/libunwind/src/ptrace/ |
H A D | _UPT_reg_offset.c | 293 UNW_R_OFF(RAX, rax)
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/external/valgrind/main/memcheck/ |
H A D | mc_machine.c | 575 if (o == GOF(RAX) && is1248) return o; 617 if (o == 1+ GOF(RAX) && szB == 1) return GOF(CC_OP); 668 /* Map high halves of %RAX,%RCX,%RDX,%RBX to the whole register. 672 if (o == 4+ GOF(RAX) && sz == 4) return GOF(RAX);
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/external/strace/ |
H A D | process.c | 1314 XLAT(8*RAX),
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