Searched refs:RAX (Results 1 - 25 of 26) sorted by relevance

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/external/kernel-headers/original/uapi/asm-x86/asm/
H A Dptrace-abi.h39 #define RAX 80 macro
/external/llvm/test/MC/X86/
H A Dintel-syntax-encoding.s25 mov QWORD PTR [RSP - 16], RAX
H A Dintel-syntax.s19 mov RAX, QWORD PTR [RSP]
25 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
65 mov RAX, QWORD PTR FS:[320]
67 mov RAX, QWORD PTR FS:320
69 mov QWORD PTR FS:320, RAX
71 mov QWORD PTR FS:20[rbx], RAX
380 shld [RAX], BX
381 shld [RAX], BX, CL
385 shrd [RAX], BX
386 shrd [RAX], B
[all...]
/external/libunwind/src/x86_64/
H A Dunwind_i.h39 #define RAX 0 macro
H A Dinit.h49 c->dwarf.loc[RAX] = REG_INIT_LOC(c, rax, RAX);
H A DGregs.c104 loc = c->dwarf.loc[(reg == UNW_X86_64_RAX) ? RAX : RDX];
H A DGos-freebsd.c111 c->dwarf.loc[RAX] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RAX, 0);
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmInstrumentation.cpp357 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
369 Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI));
370 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
371 .addReg(X86::RAX).addImm(3));
378 X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
430 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX));
438 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
444 Inst.addOperand(MCOperand::CreateReg(X86::RAX));
448 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
449 .addReg(X86::RAX)
[all...]
H A DX86Operand.h343 case X86::RAX: return X86::EAX;
H A DX86AsmParser.cpp2196 return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
/external/lzma/Asm/x86/
H A D7zAsm.asm62 r0 equ RAX
/external/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp250 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
277 if (Op0 == X86::RAX && Op1 == X86::EAX)
311 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
693 BaseReg = X86::RAX; ScaleVal = 1;
701 IndexReg = X86::RAX; break;
703 IndexReg = X86::RAX; break;
706 IndexReg = X86::RAX; break;
708 IndexReg = X86::RAX; break;
710 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
888 .addReg(X86::RAX));
[all...]
H A DX86RegisterInfo.cpp550 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
562 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
599 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
635 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
671 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
672 return X86::RAX;
H A DX86SelectionDAGInfo.cpp106 ValReg = X86::RAX;
H A DX86FrameLowering.cpp104 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
171 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
697 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
721 .addReg(X86::RAX)
1352 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1472 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
H A DX86FastISel.cpp1073 unsigned RetReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
1620 { &X86::GR64RegClass, X86::RAX, X86::RDX, {
1621 { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv
1623 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv
2438 static const unsigned Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX };
2439 // First copy the first operand into RAX, which is an implicit input to
H A DX86ISelDAGToDAG.cpp2225 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2285 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2431 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
H A DX86ISelLowering.cpp620 setExceptionPointerRegister(X86::RAX);
1933 // which is returned in RAX / RDX.
1969 X86::RAX : X86::EAX;
1973 // RAX/EAX now acts like a return value.
10379 X86::RAX, X86II::MO_TLSGD);
10395 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
10542 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13196 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
14287 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14328 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MV
[all...]
H A DX86InstrInfo.cpp5529 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5532 is64Bit ? X86::RAX : X86::EAX)
5556 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
5561 .addReg(is64Bit ? X86::RAX : X86::EAX);
/external/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h171 ENTRY(RAX) \
189 ENTRY(RAX) \
/external/valgrind/main/VEX/auxprogs/
H A Dgenoffsets.c103 GENOFFSET(AMD64,amd64,RAX);
/external/valgrind/main/coregrind/m_sigframe/
H A Dsigframe-amd64-linux.c358 SC2(rax,RAX);
/external/libunwind/src/ptrace/
H A D_UPT_reg_offset.c293 UNW_R_OFF(RAX, rax)
/external/valgrind/main/memcheck/
H A Dmc_machine.c575 if (o == GOF(RAX) && is1248) return o;
617 if (o == 1+ GOF(RAX) && szB == 1) return GOF(CC_OP);
668 /* Map high halves of %RAX,%RCX,%RDX,%RBX to the whole register.
672 if (o == 4+ GOF(RAX) && sz == 4) return GOF(RAX);
/external/strace/
H A Dprocess.c1314 XLAT(8*RAX),

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