/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.h | 40 bool isMicroMips(const MCSubtargetInfo &STI) const; 50 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, 55 const MCSubtargetInfo &STI) const override; 61 const MCSubtargetInfo &STI) const; 68 const MCSubtargetInfo &STI) const; 75 const MCSubtargetInfo &STI) const; 82 const MCSubtargetInfo &STI) const; 89 const MCSubtargetInfo &STI) const; 96 const MCSubtargetInfo &STI) const; 103 const MCSubtargetInfo &STI) cons [all...] |
H A D | MipsELFStreamer.cpp | 15 const MCSubtargetInfo &STI, bool RelaxAll, 17 return new MipsELFStreamer(Context, MAB, OS, Emitter, STI); 13 createMipsELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument
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H A D | MipsMCCodeEmitter.cpp | 38 const MCSubtargetInfo &STI, 45 const MCSubtargetInfo &STI, 116 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const { 117 return STI.getFeatureBits() & Mips::FeatureMicroMips; 125 const MCSubtargetInfo &STI, 131 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) { 132 EmitInstruction(Val >> 16, 2, STI, OS); 133 EmitInstruction(Val, 2, STI, OS); 147 const MCSubtargetInfo &STI) const 170 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 36 createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument 43 createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument [all...] |
H A D | MipsNaClELFStreamer.cpp | 40 MCCodeEmitter *Emitter, const MCSubtargetInfo &STI) 41 : MipsELFStreamer(Context, TAB, OS, Emitter, STI), PendingCall(false) {} 94 const MCSubtargetInfo &STI) { 100 MipsELFStreamer::EmitInstruction(MaskInst, STI); 105 void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) { argument 109 emitMask(AddrReg, IndirectBranchMaskReg, STI); 110 MipsELFStreamer::EmitInstruction(MI, STI); 117 const MCSubtargetInfo &STI, bool MaskBefore, 123 emitMask(BaseReg, LoadStoreStackMaskReg, STI); 125 MipsELFStreamer::EmitInstruction(MI, STI); 39 MipsNaClELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI) argument 93 emitMask(unsigned AddrReg, unsigned MaskReg, const MCSubtargetInfo &STI) argument 116 sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, const MCSubtargetInfo &STI, bool MaskBefore, bool MaskAfter) argument 254 createMipsNaClELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument [all...] |
H A D | MipsELFStreamer.h | 31 MCCodeEmitter *Emitter, const MCSubtargetInfo &STI) 39 const MCSubtargetInfo &STI, bool RelaxAll, 30 MipsELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI) argument
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H A D | MipsMCNaCl.h | 28 const MCSubtargetInfo &STI,
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 40 const MCSubtargetInfo &STI) const override; 46 const MCSubtargetInfo &STI) const; 52 const MCSubtargetInfo &STI) const; 60 const MCSubtargetInfo &STI) const; 63 const MCSubtargetInfo &STI) const; 66 const MCSubtargetInfo &STI) const; 69 const MCSubtargetInfo &STI) const; 72 const MCSubtargetInfo &STI) const; 84 const MCSubtargetInfo &STI) const { 89 const MCSubtargetInfo &STI) cons [all...] |
/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 51 const MCSubtargetInfo &STI) const; 57 const MCSubtargetInfo &STI) const; 65 const MCSubtargetInfo &STI) const; 71 const MCSubtargetInfo &STI) const; 77 const MCSubtargetInfo &STI) const; 83 const MCSubtargetInfo &STI) const; 89 const MCSubtargetInfo &STI) const; 96 const MCSubtargetInfo &STI) const; 102 const MCSubtargetInfo &STI) const; 108 const MCSubtargetInfo &STI) cons 206 createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMRegisterInfo.h | 26 ARMRegisterInfo(const ARMSubtarget &STI);
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H A D | ARMInstrInfo.h | 26 explicit ARMInstrInfo(const ARMSubtarget &STI);
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/external/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.h | 26 AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument 27 : MCDisassembler(STI, Ctx) {}
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 33 const MCSubtargetInfo &STI) const; 37 const MCSubtargetInfo &STI) const {
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H A D | AMDGPUMCTargetDesc.cpp | 70 const MCSubtargetInfo &STI) { 76 const MCSubtargetInfo &STI, 78 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { 79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); 81 return createR600MCCodeEmitter(MCII, MRI, STI); 89 const MCSubtargetInfo &STI, 65 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument 74 createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument 85 createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument
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H A D | AMDGPUMCTargetDesc.h | 36 const MCSubtargetInfo &STI); 40 const MCSubtargetInfo &STI,
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 53 bool isThumb(const MCSubtargetInfo &STI) const { 54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 56 bool isThumb2(const MCSubtargetInfo &STI) const { 57 return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0; 59 bool isTargetMachO(const MCSubtargetInfo &STI) const { 60 Triple TT(STI.getTargetTriple()); 70 const MCSubtargetInfo &STI) const; 76 const MCSubtargetInfo &STI) const; 83 const MCSubtargetInfo &STI) cons 420 createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument 427 createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument 567 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) argument [all...] |
/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 50 const MCSubtargetInfo &STI) const; 53 const MCSubtargetInfo &STI) const; 56 const MCSubtargetInfo &STI) const; 59 const MCSubtargetInfo &STI) const; 62 const MCSubtargetInfo &STI) const; 65 const MCSubtargetInfo &STI) const; 68 const MCSubtargetInfo &STI) const; 71 const MCSubtargetInfo &STI) const; 74 const MCSubtargetInfo &STI) const; 77 const MCSubtargetInfo &STI) cons 153 createPPCMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCDisassembler.h | 58 MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument 59 : Ctx(Ctx), STI(STI), Symbolizer(), CommentStream(nullptr) {} 90 const MCSubtargetInfo &STI; member in class:llvm::MCDisassembler 108 const MCSubtargetInfo& getSubtargetInfo() const { return STI; }
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 45 const MCSubtargetInfo &STI) const override; 51 const MCSubtargetInfo &STI) const; 57 const MCSubtargetInfo &STI) const; 61 const MCSubtargetInfo &STI) const; 64 const MCSubtargetInfo &STI) const; 67 const MCSubtargetInfo &STI) const; 70 const MCSubtargetInfo &STI) const; 77 const MCSubtargetInfo &STI, 85 const MCSubtargetInfo &STI) const { 86 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); 75 createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCTargetDesc.h | 32 const MCSubtargetInfo &STI, 36 const MCSubtargetInfo &STI,
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H A D | AMDGPUMCTargetDesc.cpp | 69 const MCSubtargetInfo &STI) { 74 const MCSubtargetInfo &STI, 76 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { 77 return createSIMCCodeEmitter(MCII, STI, Ctx); 79 return createR600MCCodeEmitter(MCII, STI, Ctx); 64 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument 73 createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/Mips/ |
H A D | MipsFrameLowering.h | 25 const MipsSubtarget &STI; member in class:llvm::MipsFrameLowering 29 : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {}
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCTargetDesc.h | 32 const MCSubtargetInfo &STI, 36 const MCSubtargetInfo &STI,
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H A D | AMDGPUMCTargetDesc.cpp | 69 const MCSubtargetInfo &STI) { 74 const MCSubtargetInfo &STI, 76 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { 77 return createSIMCCodeEmitter(MCII, STI, Ctx); 79 return createR600MCCodeEmitter(MCII, STI, Ctx); 64 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument 73 createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmInstrumentation.h | 31 const MCContext &Ctx, const MCSubtargetInfo &STI); 47 const MCContext &Ctx, const MCSubtargetInfo &STI);
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/external/llvm/include/llvm/CodeGen/ |
H A D | TargetSchedule.h | 37 const TargetSubtargetInfo *STI; member in class:llvm::TargetSchedModel 44 TargetSchedModel(): STI(nullptr), TII(nullptr) {} 115 return STI->getWriteProcResBegin(SC); 118 return STI->getWriteProcResEnd(SC);
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