Searched refs:ImplicitDefs (Results 1 - 13 of 13) sorted by relevance
| /external/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 147 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr member in class:llvm::MCInstrDesc
530 return ImplicitDefs;
535 if (!ImplicitDefs) return 0;
537 for (; ImplicitDefs[i]; ++i) /*empty*/;
554 if (const uint16_t *ImpDefs = ImplicitDefs)
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1367 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1392 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1420 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1444 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1469 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1492 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1519 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1546 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1562 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1579 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[
[all...] |
| H A D | ScheduleDAGFast.cpp | 437 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
515 if (!MCID.ImplicitDefs)
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| H A D | ScheduleDAGSDNodes.cpp | 126 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
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| H A D | ScheduleDAGRRList.cpp | 1195 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
1321 if (!MCID.ImplicitDefs)
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| /external/llvm/utils/TableGen/ |
| H A D | CodeGenInstruction.h | 219 /// ImplicitDefs/ImplicitUses - These are lists of registers that are
221 std::vector<Record*> ImplicitDefs, ImplicitUses; member in class:llvm::CodeGenInstruction
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| H A D | CodeGenInstruction.cpp | 332 ImplicitDefs = R->getValueAsListOfDefs("Defs");
364 if (ImplicitDefs.empty()) return MVT::Other;
367 Record *FirstImplicitDef = ImplicitDefs[0];
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| H A D | DAGISelMatcherGen.cpp | 841 HandledReg = II.ImplicitDefs[0];
964 HandledReg = II.ImplicitDefs[0];
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| H A D | CodeGenDAGPatterns.cpp | 1674 if (!InstInfo.ImplicitDefs.empty()) {
1678 // ImplicitDefs.
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 303 .addReg(II.ImplicitDefs[0]));
331 .addReg(II.ImplicitDefs[0]));
363 .addReg(II.ImplicitDefs[0]));
389 .addReg(II.ImplicitDefs[0]));
419 .addReg(II.ImplicitDefs[0]));
438 .addReg(II.ImplicitDefs[0]));
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| /external/llvm/lib/Target/R600/ |
| H A D | SIInstrInfo.cpp | 1532 if (NewDesc.ImplicitDefs) {
1533 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
1534 unsigned Reg = NewDesc.ImplicitDefs[i];
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| /external/llvm/lib/CodeGen/ |
| H A D | MachineInstr.cpp | 538 if (MCID->ImplicitDefs)
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1555 if (NewDesc.ImplicitDefs)
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