Searched refs:_NEW_STENCIL (Results 1 - 25 of 36) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/mesa/main/
H A Dstencil.c116 FLUSH_VERTICES(ctx, _NEW_STENCIL);
166 FLUSH_VERTICES(ctx, _NEW_STENCIL);
216 FLUSH_VERTICES(ctx, _NEW_STENCIL);
237 FLUSH_VERTICES(ctx, _NEW_STENCIL);
278 FLUSH_VERTICES(ctx, _NEW_STENCIL);
293 FLUSH_VERTICES(ctx, _NEW_STENCIL);
349 FLUSH_VERTICES(ctx, _NEW_STENCIL);
370 FLUSH_VERTICES(ctx, _NEW_STENCIL);
402 FLUSH_VERTICES(ctx, _NEW_STENCIL);
451 FLUSH_VERTICES(ctx, _NEW_STENCIL);
[all...]
H A Dstate.c513 if (new_state & (_NEW_STENCIL | _NEW_BUFFERS))
536 | _NEW_STENCIL | _MESA_NEW_SEPARATE_SPECULAR))
/external/mesa3d/src/mesa/main/
H A Dstencil.c116 FLUSH_VERTICES(ctx, _NEW_STENCIL);
166 FLUSH_VERTICES(ctx, _NEW_STENCIL);
216 FLUSH_VERTICES(ctx, _NEW_STENCIL);
237 FLUSH_VERTICES(ctx, _NEW_STENCIL);
278 FLUSH_VERTICES(ctx, _NEW_STENCIL);
293 FLUSH_VERTICES(ctx, _NEW_STENCIL);
349 FLUSH_VERTICES(ctx, _NEW_STENCIL);
370 FLUSH_VERTICES(ctx, _NEW_STENCIL);
402 FLUSH_VERTICES(ctx, _NEW_STENCIL);
451 FLUSH_VERTICES(ctx, _NEW_STENCIL);
[all...]
H A Dstate.c513 if (new_state & (_NEW_STENCIL | _NEW_BUFFERS))
536 | _NEW_STENCIL | _MESA_NEW_SEPARATE_SPECULAR))
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dgen6_depthstencil.c47 /* _NEW_STENCIL */
96 .mesa = _NEW_DEPTH | _NEW_STENCIL | _NEW_BUFFERS,
H A Dbrw_vtbl.c127 * _NEW_BUFFERS | _NEW_STENCIL, but i965 code assumes that the value
128 * only changes with _NEW_STENCIL (which seems sensible). So flag it
131 intel->NewGLState |= (_NEW_DEPTH | _NEW_STENCIL);
H A Dgen7_misc_state.c114 /* _NEW_STENCIL: enable stencil buffer writes */
189 /* _NEW_DEPTH, _NEW_STENCIL */
284 .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
H A Dbrw_cc.c106 /* _NEW_STENCIL */
232 .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH,
H A Dgen6_cc.c224 /* _NEW_STENCIL */
239 .mesa = _NEW_COLOR | _NEW_STENCIL,
H A Dbrw_state_upload.c343 DEFINE_BIT(_NEW_STENCIL),
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dgen6_depthstencil.c47 /* _NEW_STENCIL */
96 .mesa = _NEW_DEPTH | _NEW_STENCIL | _NEW_BUFFERS,
H A Dbrw_vtbl.c127 * _NEW_BUFFERS | _NEW_STENCIL, but i965 code assumes that the value
128 * only changes with _NEW_STENCIL (which seems sensible). So flag it
131 intel->NewGLState |= (_NEW_DEPTH | _NEW_STENCIL);
H A Dgen7_misc_state.c114 /* _NEW_STENCIL: enable stencil buffer writes */
189 /* _NEW_DEPTH, _NEW_STENCIL */
284 .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
H A Dbrw_cc.c106 /* _NEW_STENCIL */
232 .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH,
H A Dgen6_cc.c224 /* _NEW_STENCIL */
239 .mesa = _NEW_COLOR | _NEW_STENCIL,
H A Dbrw_state_upload.c343 DEFINE_BIT(_NEW_STENCIL),
/external/chromium_org/third_party/mesa/src/src/mesa/state_tracker/
H A Dst_atom_depth.c156 (_NEW_DEPTH|_NEW_STENCIL|_NEW_COLOR), /* mesa */
/external/mesa3d/src/mesa/state_tracker/
H A Dst_atom_depth.c156 (_NEW_DEPTH|_NEW_STENCIL|_NEW_COLOR), /* mesa */
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i915/
H A Di915_context.c73 if (new_state & (_NEW_STENCIL | _NEW_BUFFERS | _NEW_POLYGON))
/external/chromium_org/third_party/mesa/src/src/mesa/swrast/
H A Ds_context.h108 _NEW_STENCIL| \
/external/mesa3d/src/mesa/drivers/dri/i915/
H A Di915_context.c73 if (new_state & (_NEW_STENCIL | _NEW_BUFFERS | _NEW_POLYGON))
/external/mesa3d/src/mesa/swrast/
H A Ds_context.h108 _NEW_STENCIL| \
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
H A Dradeon_common.c294 ctx->NewState |= _NEW_STENCIL;
315 ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL);
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
H A Dradeon_common.c294 ctx->NewState |= _NEW_STENCIL;
315 ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL);
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dradeon_common.c294 ctx->NewState |= _NEW_STENCIL;
315 ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL);

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