/external/srec/config/en.us/dictionary/ |
H A D | c0.6 | [all...] |
/external/owasp/sanitizer/lib/htmlparser-1.3/ |
H A D | htmlparser-1.3-with-transitions.jar | META-INF/MANIFEST.MF nu/validator/htmlparser/tools/XSLT4HTML5XOM.class XSLT4HTML5XOM.java package nu. ... |
H A D | htmlparser-1.3.jar | META-INF/MANIFEST.MF nu/validator/htmlparser/tools/XSLT4HTML5XOM.class XSLT4HTML5XOM.java package nu. ... |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUAsmPrinter.cpp | 66 MachineInstr &MI = *I; local 68 unsigned numOperands = MI.getNumOperands(); 70 MachineOperand & MO = MI.getOperand(op_idx);
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H A D | AMDGPUAsmPrinter.h | 38 virtual void EmitInstruction(const MachineInstr *MI);
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H A D | AMDGPUCodeEmitter.h | 21 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 22 virtual uint64_t getMachineOpValue(const MachineInstr &MI, argument 24 virtual unsigned GPR4AlignEncode(const MachineInstr &MI, argument 28 virtual unsigned GPR2AlignEncode(const MachineInstr &MI, argument 32 virtual uint64_t VOPPostEncode(const MachineInstr &MI, argument 36 virtual uint64_t i32LiteralEncode(const MachineInstr &MI, argument 40 virtual uint32_t SMRDmemriEncode(const MachineInstr &MI, unsigned OpNo) argument
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H A D | AMDGPUConvertToISA.cpp | 57 MachineInstr &MI = *I; local 58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
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H A D | AMDGPUInstrInfo.cpp | 36 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, argument 43 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, argument 49 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, argument 55 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, argument 61 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, argument 66 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, argument 71 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, argument 123 MachineBasicBlock::iterator MI, 133 MachineBasicBlock::iterator MI, 142 MachineInstr *MI, 122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 141 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, int FrameIndex) const argument 149 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, MachineInstr *LoadMI) const argument 157 canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops) const argument 164 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 221 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument 238 convertToISA(MachineInstr & MI, MachineFunction &MF, DebugLoc DL) const argument [all...] |
H A D | AMDGPUInstrInfo.h | 51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, 54 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 55 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 57 bool hasLoadFromStackSlot(const MachineInstr *MI, 60 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 61 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI, 63 bool hasStoreFromStackSlot(const MachineInstr *MI, 74 MachineBasicBlock::iterator MI, DebugLoc DL, 79 MachineBasicBlock::iterator MI, 84 MachineBasicBlock::iterator MI, [all...] |
H A D | AMDGPUMCInstLower.cpp | 30 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { argument 31 OutMI.setOpcode(MI->getOpcode()); 33 for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) { 34 const MachineOperand &MO = MI->getOperand(i); 58 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { argument 62 if (MI->getOpcode() == AMDGPU::MASK_WRITE) { 66 if (MI->isBundle()) { 67 const MachineBasicBlock *MBB = MI->getParent(); 68 MachineBasicBlock::const_instr_iterator I = MI; 79 MCInstLowering.lower(MI, TmpIns [all...] |
H A D | AMDGPUMCInstLower.h | 24 void lower(const MachineInstr *MI, MCInst &OutMI) const;
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H A D | AMDGPURegisterInfo.cpp | 38 void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, argument
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H A D | AMDGPURegisterInfo.h | 54 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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H A D | R600ExpandSpecialInstrs.cpp | 60 MachineInstr &MI = *I; local 63 bool IsReduction = TII->isReductionOp(MI.getOpcode()); 64 bool IsVector = TII->isVector(MI); 65 bool IsCube = TII->isCubeOp(MI.getOpcode()); 96 unsigned DstReg = MI.getOperand(0).getReg(); 97 unsigned Src0 = MI.getOperand(1).getReg(); 102 Src1 = MI.getOperand(2).getReg(); 135 switch (MI.getOpcode()) { 148 Opcode = MI.getOpcode(); 159 MI [all...] |
H A D | R600ISelLowering.cpp | 54 MachineInstr * MI, MachineBasicBlock * BB) const 58 MachineBasicBlock::iterator I = *MI; 60 switch (MI->getOpcode()) { 61 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 66 .addOperand(MI->getOperand(0)) 67 .addOperand(MI->getOperand(1)) 77 .addOperand(MI->getOperand(0)) 78 .addOperand(MI->getOperand(1)) 89 .addOperand(MI->getOperand(0)) 90 .addOperand(MI 53 EmitInstrWithCustomInserter( MachineInstr * MI, MachineBasicBlock * BB) const argument [all...] |
H A D | R600ISelLowering.h | 27 virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, 41 void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
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H A D | R600InstrInfo.cpp | 38 bool R600InstrInfo::isTrig(const MachineInstr &MI) const 40 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG; 43 bool R600InstrInfo::isVector(const MachineInstr &MI) const 45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; 50 MachineBasicBlock::iterator MI, DebugLoc DL, 58 BuildMI(MBB, MI, DL, get(AMDGPU::MOV)) 71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg) 81 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc()); local 82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 83 MachineInstrBuilder(MI) 49 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 168 MachineInstr *MI = I; local 251 const MachineInstr *MI = op.getParent(); local 439 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument 455 PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const argument 470 getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost) const argument 498 addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const argument 505 clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const argument [all...] |
H A D | R600InstrInfo.h | 44 MachineBasicBlock::iterator MI, DebugLoc DL, 48 bool isTrig(const MachineInstr &MI) const; 55 bool isVector(const MachineInstr &MI) const; 75 bool isPredicated(const MachineInstr *MI) const; 77 bool isPredicable(MachineInstr *MI) const; 94 bool DefinesPredicate(MachineInstr *MI, 103 bool PredicateInstruction(MachineInstr *MI, 107 const MachineInstr *MI, 115 bool hasFlagOperand(const MachineInstr &MI) const; 118 void addFlag(MachineInstr *MI, unsigne [all...] |
H A D | SIISelLowering.cpp | 66 MachineInstr * MI, MachineBasicBlock * BB) const 70 MachineBasicBlock::iterator I = MI; 72 if (TII->get(MI->getOpcode()).TSFlags & SIInstrFlags::NEED_WAIT) { 73 AppendS_WAITCNT(MI, *BB, llvm::next(I)); 77 switch (MI->getOpcode()) { 79 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 83 .addOperand(MI->getOperand(0)) 84 .addOperand(MI->getOperand(1)) 87 .addOperand(MI->getOperand(1)) 88 .addOperand(MI 65 EmitInstrWithCustomInserter( MachineInstr * MI, MachineBasicBlock * BB) const argument 142 AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I) const argument 149 LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const argument 181 LowerSI_INTERP_CONST(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const argument 203 LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const argument 235 LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const argument [all...] |
H A D | SIISelLowering.h | 30 void AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB, 32 void LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB, 34 void LowerSI_INTERP_CONST(MachineInstr *MI, MachineBasicBlock &BB, 36 void LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB, 38 void LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, 49 virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
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/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 7 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument 9 printInstruction(MI, OS); 14 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument 17 const MCOperand &Op = MI->getOperand(OpNo); 29 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, argument 31 printOperand(MI, OpNo, O);
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H A D | AMDGPUInstPrinter.h | 18 void printInstruction(const MCInst *MI, raw_ostream &O); 22 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); 25 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 26 // void printUnsignedImm(const MCInst *MI, int OpNo, raw_ostream &O); 27 void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 28 uint64_t getBinaryCodeForInstr(const MCInst &MI, 31 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, argument 36 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, argument 40 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, argument 44 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const { argument 47 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo, argument 51 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, argument
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H A D | R600MCCodeEmitter.cpp | 53 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 61 void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, 63 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const; 64 void EmitDst(const MCInst &MI, raw_ostream &OS) const; 65 void EmitALU(const MCInst &MI, unsigned numSrc, 68 void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, 70 void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const; 87 bool isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const; 150 void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostrea argument 192 EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument 234 EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const argument 298 EmitDst(const MCInst &MI, raw_ostream &OS) const argument 330 EmitALU(const MCInst &MI, unsigned numSrc, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument 393 EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument 485 EmitFCInstr(const MCInst &MI, raw_ostream &OS) const argument 620 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixup) const argument 674 isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const argument [all...] |
H A D | SIMCCodeEmitter.cpp | 74 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 84 unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const; 87 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, 91 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, 96 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo, 100 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, 104 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const; 109 unsigned getEncodingType(const MCInst &MI) const; 112 unsigned getEncodingBytes(const MCInst &MI) cons 131 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const argument 140 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups) const argument 161 GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const argument 167 GPR2AlignEncode(const MCInst &MI, unsigned OpNo , SmallVectorImpl<MCFixup> &Fixup) const argument 173 GPR4AlignEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument 179 i32LiteralEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument 197 SMRDmemriEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument 219 VOPPostEncode(const MCInst &MI, uint64_t Value) const argument [all...] |