Searched refs:enableMachineScheduler (Results 1 - 12 of 12) sorted by relevance

/external/llvm/lib/Target/
H A DTargetSubtargetInfo.cpp30 bool TargetSubtargetInfo::enableMachineScheduler() const { function in class:TargetSubtargetInfo
35 return enableMachineScheduler();
/external/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp99 bool HexagonSubtarget::enableMachineScheduler() const { function in class:HexagonSubtarget
H A DHexagonSubtarget.h88 bool enableMachineScheduler() const override;
/external/llvm/include/llvm/Target/
H A DTargetSubtargetInfo.h106 virtual bool enableMachineScheduler() const;
/external/llvm/lib/Target/AArch64/
H A DAArch64Subtarget.h92 bool enableMachineScheduler() const override { return true; }
/external/llvm/lib/Target/R600/
H A DAMDGPUSubtarget.h223 bool enableMachineScheduler() const override {
/external/llvm/lib/Target/PowerPC/
H A DPPCSubtarget.cpp170 bool PPCSubtarget::enableMachineScheduler() const { function in class:PPCSubtarget
H A DPPCSubtarget.h275 bool enableMachineScheduler() const override;
H A DPPCISelLowering.cpp892 if (Subtarget.enableMachineScheduler())
11240 if (DisableILPPref || Subtarget.enableMachineScheduler())
/external/llvm/lib/Target/X86/
H A DX86Subtarget.h484 bool enableMachineScheduler() const override { return true; }
/external/llvm/lib/CodeGen/
H A DMachineScheduler.cpp315 } else if (!mf.getSubtarget().enableMachineScheduler())
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGISel.cpp297 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||

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