Searched refs:r_base (Results 1 - 19 of 19) sorted by relevance

/art/compiler/dex/quick/arm/
H A Dutility_arm.cc422 LIR* ArmMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { argument
423 UNUSED(r_dest, r_base, offset, move_type);
428 LIR* ArmMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { argument
429 UNUSED(r_base, offset, r_src, move_type);
748 LIR* ArmMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, argument
750 bool all_low_regs = r_base.Low8() && r_index.Low8() && r_dest.Low8();
778 NewLIR4(kThumb2AddRRR, reg_ptr.GetReg(), r_base.GetReg(), r_index.GetReg(),
781 OpRegRegReg(kOpAdd, reg_ptr, r_base, r_index);
807 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg());
809 load = NewLIR4(opcode, r_dest.GetReg(), r_base
814 StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, OpSize size) argument
880 LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base, int displacement, RegStorage r_src_dest, RegStorage r_work) argument
910 LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size) argument
1030 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument
1060 StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size) argument
1172 StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, VolatileKind is_volatile) argument
1246 OpMem(OpKind op, RegStorage r_base, int disp) argument
[all...]
H A Dcodegen_arm.h71 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
73 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
77 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
79 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
206 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
213 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
214 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
219 LIR* OpVldm(RegStorage r_base, int count);
220 LIR* OpVstm(RegStorage r_base, int count);
223 LIR* LoadBaseDispBody(RegStorage r_base, in
[all...]
H A Dcall_arm.cc45 * adr r_base, <table>
49 * ldmia r_base!, {r_key, r_disp}
69 RegStorage r_base = AllocTemp(); local
80 NewLIR3(kThumb2Adr, r_base.GetReg(), 0, WrapPointer(tab_rec));
87 NewLIR2(kThumb2LdmiaWB, r_base.GetReg(), (1 << r_key.GetRegNum()) | (1 << r_disp.GetRegNum()));
H A Dint_arm.cc1127 LIR* ArmMir2Lir::OpVldm(RegStorage r_base, int count) { argument
1128 return NewLIR3(kThumb2Vldms, r_base.GetReg(), rs_fr0.GetReg(), count);
1131 LIR* ArmMir2Lir::OpVstm(RegStorage r_base, int count) { argument
1132 return NewLIR3(kThumb2Vstms, r_base.GetReg(), rs_fr0.GetReg(), count);
/art/compiler/dex/quick/mips/
H A Dutility_mips.cc523 LIR* MipsMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, argument
525 UNUSED(r_dest, r_base, offset, move_type);
530 LIR* MipsMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { argument
531 UNUSED(r_base, offset, r_src, move_type);
569 LIR* MipsMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, argument
589 first = NewLIR3(kMips64Daddu, t_reg.GetReg() , r_base.GetReg(), r_index.GetReg());
591 first = NewLIR3(kMipsAddu, t_reg.GetReg() , r_base.GetReg(), r_index.GetReg());
595 NewLIR3(kMips64Daddu, t_reg.GetReg() , r_base.GetReg(), t_reg.GetReg());
599 first = NewLIR3(kMipsAddu, t_reg.GetReg() , r_base.GetReg(), r_index.GetReg());
602 NewLIR3(kMipsAddu, t_reg.GetReg() , r_base
643 StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, OpSize size) argument
690 LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size) argument
851 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument
875 StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size) argument
1004 StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, VolatileKind is_volatile) argument
1034 OpMem(OpKind op, RegStorage r_base, int disp) argument
[all...]
H A Dcodegen_mips.h83 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
85 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
90 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
92 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
94 LIR* GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest);
95 LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src);
203 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
210 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
211 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
216 LIR* OpVldm(RegStorage r_base, in
[all...]
H A Dcall_mips.cc58 * addiu r_base, rRA, <table> - <BaseLabel> ; table relative to BaseLabel
59 addu r_end, r_end, r_base ; end of table
62 * beq r_base, r_end, done
63 * lw r_key, 0(r_base)
64 * addu r_base, 8
66 * lw r_disp, -4(r_base)
108 RegStorage r_base = AllocPtrSizeTemp(); local
109 NewLIR4(kMipsDelta, r_base.GetReg(), 0, WrapPointer(base_label), WrapPointer(tab_rec));
110 OpRegRegReg(kOpAdd, r_end, r_end, r_base);
118 LIR* exit_branch = OpCmpBranch(kCondEq, r_base, r_en
197 RegStorage r_base = AllocPtrSizeTemp(); local
[all...]
H A Dint_mips.cc417 LIR* MipsMir2Lir::OpVldm(RegStorage r_base, int count) { argument
418 UNUSED(r_base, count);
423 LIR* MipsMir2Lir::OpVstm(RegStorage r_base, int count) { argument
424 UNUSED(r_base, count);
H A Dtarget_mips.cc789 LIR* MipsMir2Lir::GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest) { argument
797 OpRegRegImm(kOpAdd, reg_ptr, r_base, displacement);
811 LIR* MipsMir2Lir::GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src) { argument
821 OpRegRegImm(kOpAdd, temp_ptr, r_base, displacement);
/art/compiler/dex/quick/x86/
H A Dutility_x86.cc257 LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { argument
258 DCHECK(!r_base.IsFloat());
306 return NewLIR3(opcode, dest, r_base.GetReg(), offset);
309 LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { argument
310 DCHECK(!r_base.IsFloat());
359 return NewLIR3(opcode, r_base.GetReg(), offset, src);
370 LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) { argument
390 LIR *l = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), offset);
392 DCHECK_EQ(r_base, cu_->target64 ? rs_rX86_SP_64 : rs_rX86_SP_32);
556 LIR* X86Mir2Lir::OpMem(OpKind op, RegStorage r_base, in argument
643 LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, RegStorage r_dest, OpSize size) argument
771 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument
776 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument
791 StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, RegStorage r_src, OpSize size, int opt_flags) argument
905 StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, OpSize size) argument
910 StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, VolatileKind is_volatile) argument
[all...]
H A Dcodegen_x86.h92 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
94 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
99 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
101 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
302 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
309 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE;
310 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE;
315 LIR* OpVldm(RegStorage r_base, int count) OVERRIDE;
316 LIR* OpVstm(RegStorage r_base, int count) OVERRIDE;
429 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorag
[all...]
H A Dint_x86.cc1091 void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { argument
1092 NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset);
1452 LIR* X86Mir2Lir::OpVldm(RegStorage r_base, int count) { argument
1453 UNUSED(r_base, count);
1458 LIR* X86Mir2Lir::OpVstm(RegStorage r_base, int count) { argument
1459 UNUSED(r_base, count);
1976 int r_base = rs_rX86_SP_32.GetReg(); local
1981 r_base, displacement + LOWORD_OFFSET);
1986 lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET);
2019 int r_base local
2869 int r_base = rs_rX86_SP_32.GetReg(); local
2900 int r_base = rs_rX86_SP_32.GetReg(); local
[all...]
H A Dtarget_x86.cc905 int r_base = rs_rX86_SP_32.GetReg(); local
909 LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo);
912 store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi);
/art/compiler/dex/quick/arm64/
H A Dutility_arm64.cc675 LIR* Arm64Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, argument
677 UNUSED(r_dest, r_base, offset, move_type);
682 LIR* Arm64Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, argument
684 UNUSED(r_base, offset, r_src, move_type);
1024 LIR* Arm64Mir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, argument
1029 r_base = Check64BitReg(r_base);
1052 return NewLIR4(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(),
1099 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg());
1102 load = NewLIR4(opcode, r_dest.GetReg(), r_base
1109 StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, OpSize size) argument
1191 LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size) argument
1272 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument
1287 StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size) argument
1362 StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, VolatileKind is_volatile) argument
1390 OpMem(OpKind op, RegStorage r_base, int disp) argument
[all...]
H A Dcodegen_arm64.h67 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
69 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
73 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
75 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
209 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
216 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE;
217 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE;
222 LIR* OpVldm(RegStorage r_base, int count) OVERRIDE;
223 LIR* OpVstm(RegStorage r_base, int count) OVERRIDE;
384 LIR* LoadBaseDispBody(RegStorage r_base, in
[all...]
H A Dcall_arm64.cc41 * adr r_base, <table>
46 * ldp r_key, r_disp, [r_base], #8
50 * adr r_base, #0 ; This is the instruction from which we compute displacements
51 * add r_base, r_disp
52 * br r_base
68 RegStorage r_base = AllocTempWide(); local
73 NewLIR3(kA64Adr2xd, r_base.GetReg(), 0, WrapPointer(tab_rec));
83 NewLIR4(kA64LdpPost4rrXD, r_key.GetReg(), r_disp.GetReg(), r_base.GetReg(), 2);
91 LIR* switch_label = NewLIR3(kA64Adr2xd, r_base.GetReg(), 0, -1);
95 OpRegRegRegExtend(kOpAdd, r_base, r_bas
[all...]
H A Dint_arm64.cc966 LIR* Arm64Mir2Lir::OpVldm(RegStorage r_base, int count) { argument
967 UNUSED(r_base, count);
972 LIR* Arm64Mir2Lir::OpVstm(RegStorage r_base, int count) { argument
973 UNUSED(r_base, count);
/art/compiler/dex/quick/
H A Dmir_to_lir.h976 LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { argument
977 return LoadBaseDisp(r_base, displacement, r_dest, kWord, kNotVolatile);
980 LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { argument
981 return LoadBaseDisp(r_base, displacement, r_dest, k32, kNotVolatile);
984 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, argument
986 return LoadBaseDisp(r_base, displacement, r_dest, kReference, is_volatile);
989 LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale) { argument
990 return LoadBaseIndexed(r_base, r_index, r_dest, scale, kReference);
1005 LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src) { argument
1006 return StoreBaseDisp(r_base, displacemen
1009 StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, VolatileKind is_volatile) argument
1014 StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) argument
1018 Store32Disp(RegStorage r_base, int displacement, RegStorage r_src) argument
[all...]
H A Dgen_common.cc96 RegStorage r_base = TargetReg(kArg0, kRef); local
97 LockTemp(r_base);
100 OpPcRelDexCacheArrayLoad(cu_->dex_file, offset, r_base, false);
103 RegStorage r_method = LoadCurrMethodWithHint(r_base);
104 LoadRefDisp(r_method, ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base,
107 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile);
109 // r_base now points at static storage (Class*) or null if the type is not yet resolved.
112 // Check if r_base is null.
113 unresolved_branch = OpCmpImmBranch(kCondEq, r_base,
691 RegStorage r_base; local
769 RegStorage r_base; local
[all...]

Completed in 5342 milliseconds