/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 36 if (getOpcode() < ISD::BUILTIN_OP_END) 54 case ISD::DELETED_NODE: return "<<Deleted Node!>>"; 56 case ISD::PREFETCH: return "Prefetch"; 57 case ISD::ATOMIC_FENCE: return "AtomicFence"; 58 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 59 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess"; 60 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 61 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 62 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 63 case ISD [all...] |
H A D | LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition 16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC; 22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR, 199 if (Op.getOpcode() == ISD::LOAD) { 201 ISD::LoadExtType ExtType = LD->getExtensionType(); 202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) 228 } else if (Op.getOpcode() == ISD::STORE) { 260 case ISD::ADD: 261 case ISD [all...] |
H A D | LegalizeIntegerTypes.cpp | 52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; 53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; 56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 59 case ISD::CONVERT_RNDSAT: 61 case ISD::CTLZ_ZERO_UNDEF: 62 case ISD [all...] |
H A D | DAGCombiner.cpp | 136 if (N->getOpcode() == ISD::HANDLENODE) 192 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed 195 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced. 213 ISD::NodeType ExtType); 321 SDValue N3, ISD::CondCode CC, 323 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 519 if (Op.getOpcode() == ISD::FNEG) return 2; 529 case ISD::ConstantFP: 533 case ISD::FADD: 539 !TLI.isOperationLegalOrCustom(ISD [all...] |
H A D | TargetLowering.cpp | 122 ISD::CondCode &CCCode, 130 case ISD::SETEQ: 131 case ISD::SETOEQ: 135 case ISD::SETNE: 136 case ISD::SETUNE: 140 case ISD::SETGE: 141 case ISD::SETOGE: 145 case ISD::SETLT: 146 case ISD::SETOLT: 150 case ISD [all...] |
H A D | LegalizeDAG.cpp | 263 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && 276 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, 293 assert(ST->getAddressingMode() == ISD::UNINDEXED && 310 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); 351 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 353 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 363 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 375 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); 391 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 399 Ptr = DAG.getNode(ISD [all...] |
H A D | LegalizeVectorTypes.cpp | 51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; 52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; 54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 60 case ISD [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 88 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 89 assert(ISD && "Invalid opcode"); 91 if (ISD == ISD::SDIV && 114 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 115 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 116 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 117 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 122 int Idx = CostTableLookup(AVX2UniformConstCostTable, ISD, LT.second); 128 { ISD 458 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 668 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 888 int ISD = TLI->InstructionOpcodeToISD(Opcode); local [all...] |
H A D | X86CallingConv.h | 26 ISD::ArgFlagsTy &ArgFlags, 37 CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
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/external/llvm/include/llvm/Target/ |
H A D | CostTable.h | 23 int ISD; member in struct:llvm::CostTblEntry 30 int CostTableLookup(const CostTblEntry<TypeTy> *Tbl, unsigned len, int ISD, argument 33 if (ISD == Tbl[i].ISD && Ty == Tbl[i].Type) 42 int CostTableLookup(const CostTblEntry<TypeTy>(&Tbl)[N], int ISD, member in namespace:llvm 44 return CostTableLookup(Tbl, N, ISD, Ty); 50 int ISD; member in struct:llvm::TypeConversionCostTblEntry 60 unsigned len, int ISD, CompareTy Dst, 63 if (ISD == Tbl[i].ISD 59 ConvertCostTableLookup(const TypeConversionCostTblEntry<TypeTy> *Tbl, unsigned len, int ISD, CompareTy Dst, CompareTy Src) argument 74 int ISD, CompareTy Dst, CompareTy Src) { member in namespace:llvm [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 51 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 52 assert(ISD && "Invalid opcode"); 57 { ISD::FP_ROUND, MVT::v2f64, 2 }, 58 { ISD::FP_EXTEND, MVT::v2f32, 2 }, 59 { ISD::FP_EXTEND, MVT::v4f32, 4 } 62 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || 63 ISD == ISD::FP_EXTEND)) { 65 int Idx = CostTableLookup(NEONFltDblTbl, ISD, L 271 int ISD = TLI->InstructionOpcodeToISD(Opcode); local [all...] |
H A D | ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl; 27 case ISD::SRL: return ARM_AM::lsr; 28 case ISD::SRA: return ARM_AM::asr; 29 case ISD::ROTR: return ARM_AM::ror; 30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCCallingConv.h | 24 CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 76 ISD::ArgFlagsTy ArgFlags, CCState &State) { 108 setOperationAction(ISD::Constant, MVT::i32, Legal); 109 setOperationAction(ISD::Constant, MVT::i64, Legal); 110 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); 111 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); 113 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 114 setOperationAction(ISD::BRIND, MVT::Other, Expand); 117 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 121 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 122 setOperationAction(ISD [all...] |
H A D | SIISelLowering.cpp | 65 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); 66 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand); 67 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); 68 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); 70 setOperationAction(ISD::ADD, MVT::i32, Legal); 71 setOperationAction(ISD::ADDC, MVT::i32, Legal); 72 setOperationAction(ISD::ADDE, MVT::i32, Legal); 73 setOperationAction(ISD::SUBC, MVT::i32, Legal); 74 setOperationAction(ISD::SUBE, MVT::i32, Legal); 76 setOperationAction(ISD [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILISelLowering.cpp | 110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); 111 setOperationAction(ISD::SUBE, VT, Expand); 112 setOperationAction(ISD::SUBC, VT, Expand); 113 setOperationAction(ISD::ADDE, VT, Expand); 114 setOperationAction(ISD::ADDC, VT, Expand); 115 setOperationAction(ISD::BRCOND, VT, Custom); 116 setOperationAction(ISD::BR_JT, VT, Expand); 117 setOperationAction(ISD::BRIND, VT, Expand); 119 setOperationAction(ISD::SREM, VT, Expand); 120 setOperationAction(ISD [all...] |
H A D | AMDGPUISelLowering.cpp | 31 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 35 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 36 setOperationAction(ISD::FEXP2, MVT::f32, Legal); 37 setOperationAction(ISD::FRINT, MVT::f32, Legal); 39 setOperationAction(ISD::UDIV, MVT::i32, Expand); 40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 41 setOperationAction(ISD::UREM, MVT::i32, Expand); 52 const SmallVectorImpl<ISD::InputArg> &Ins, 68 const SmallVectorImpl<ISD::OutputArg> &Outs, 89 case ISD [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 181 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 182 assert(ISD && "Invalid opcode"); 192 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 193 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 194 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 195 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 196 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 197 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 200 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, 201 { ISD 294 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 352 int ISD = TLI->InstructionOpcodeToISD(Opcode); local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 67 ISD::ArgFlagsTy ArgFlags, CCState &State); 72 ISD::ArgFlagsTy ArgFlags, CCState &State); 77 ISD::ArgFlagsTy ArgFlags, CCState &State); 82 ISD::ArgFlagsTy ArgFlags, CCState &State); 87 ISD::ArgFlagsTy ArgFlags, CCState &State); 92 ISD::ArgFlagsTy ArgFlags, CCState &State); 97 ISD::ArgFlagsTy ArgFlags, CCState &State) { 147 ISD::ArgFlagsTy ArgFlags, CCState &State) { 191 ISD::ArgFlagsTy ArgFlags, CCState &State) { 209 ISD [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsCCState.h | 33 void PreAnalyzeCallResultForF128(const SmallVectorImpl<ISD::InputArg> &Ins, 38 void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs); 43 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 50 PreAnalyzeFormalArgumentsForF128(const SmallVectorImpl<ISD::InputArg> &Ins); 59 /// See ISD::OutputArg::IsFixed, 73 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 87 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 90 SmallVectorImpl<ISD::ArgFlagsTy> &Flags, 93 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, 101 void AnalyzeCallResult(const SmallVectorImpl<ISD [all...] |
H A D | MipsSEISelLowering.cpp | 52 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); 53 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); 54 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); 66 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 69 setOperationAction(ISD::ADD, VecTys[i], Legal); 70 setOperationAction(ISD::SUB, VecTys[i], Legal); 71 setOperationAction(ISD::LOAD, VecTys[i], Legal); 72 setOperationAction(ISD::STORE, VecTys[i], Legal); 73 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 76 setTargetDAGCombine(ISD [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 65 namespace ISD { namespace in namespace:llvm 85 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 90 /// and all operands of the specified node are ISD::UNDEF. 92 } // end llvm:ISD namespace 383 /// are the opcode values in the ISD and <target>ISD namespaces. For 388 /// \<target\>ISD namespace). 389 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; } 392 /// memory-referencing opcode (in the \<target\>ISD namespace and 395 return NodeType >= ISD 2086 namespace ISD { namespace [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXTargetTransformInfo.cpp | 99 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 101 switch (ISD) { 105 case ISD::ADD: 106 case ISD::MUL: 107 case ISD::XOR: 108 case ISD::OR: 109 case ISD::AND:
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 81 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 82 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 85 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 86 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 87 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 88 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 89 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); 95 setOperationAction(ISD::SRA, MVT::i8, Custom); 96 setOperationAction(ISD::SHL, MVT::i8, Custom); 97 setOperationAction(ISD [all...] |
/external/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 157 /// getFCmpCondCode - Return the ISD condition code corresponding to 161 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { 163 case FCmpInst::FCMP_FALSE: return ISD::SETFALSE; 164 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ; 165 case FCmpInst::FCMP_OGT: return ISD::SETOGT; 166 case FCmpInst::FCMP_OGE: return ISD::SETOGE; 167 case FCmpInst::FCMP_OLT: return ISD::SETOLT; 168 case FCmpInst::FCMP_OLE: return ISD::SETOLE; 169 case FCmpInst::FCMP_ONE: return ISD::SETONE; 170 case FCmpInst::FCMP_ORD: return ISD [all...] |