| /external/llvm/lib/Transforms/Utils/ |
| H A D | BasicBlockUtils.cpp | 784 BasicBlock *Pred1 = nullptr; local
790 Pred1 = SomePHI->getIncomingBlock(0);
796 Pred1 = *PI++;
806 BranchInst *Pred1Br = dyn_cast<BranchInst>(Pred1->getTerminator());
821 std::swap(Pred1, Pred2);
836 IfTrue = Pred1;
841 IfFalse = Pred1;
854 BasicBlock *CommonPred = Pred1->getSinglePredecessor();
863 if (BI->getSuccessor(0) == Pred1) {
864 IfTrue = Pred1;
[all...] |
| H A D | SimplifyCFG.cpp | 1215 BasicBlock *Pred1 = *PI++;
1218 BasicBlock *BB2 = (Pred0 == BB1) ? Pred1 : Pred0;
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | R600InstrInfo.h | 97 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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| H A D | AMDGPUInstrInfo.cpp | 214 AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, argument
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| H A D | AMDGPUInstrInfo.h | 117 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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| H A D | R600InstrInfo.cpp | 447 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, argument
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| /external/llvm/lib/Target/R600/ |
| H A D | AMDGPUInstrInfo.h | 126 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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| H A D | AMDGPUInstrInfo.cpp | 240 AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, argument
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| H A D | R600InstrInfo.h | 191 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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| H A D | R600InstrInfo.cpp | 1003 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, argument
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| /external/llvm/lib/Transforms/Scalar/ |
| H A D | MergedLoadStoreMotion.cpp | 533 BasicBlock *Pred1 = *PI; local
536 if (Pred0 == Pred1)
542 int Size1 = Pred1->size();
561 if (StoreInst *S1 = canSinkFromBlock(Pred1, S0)) {
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 148 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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| H A D | HexagonInstrInfo.cpp | 1123 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, argument
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 216 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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| H A D | PPCInstrInfo.cpp | 1298 const SmallVectorImpl<MachineOperand> &Pred1,
1300 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1303 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1309 if (Pred1[1].getReg() != Pred2[1].getReg())
1312 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1297 SubsumesPredicate( const SmallVectorImpl<MachineOperand> &Pred1, const SmallVectorImpl<MachineOperand> &Pred2) const argument
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| /external/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1494 ICmpInst::Predicate Pred0, Pred1; local
1505 if (!match(Op1, m_ICmp(Pred1, m_Specific(V), m_Specific(CI1))))
1519 if (Pred0 == ICmpInst::ICMP_ULT && Pred1 == ICmpInst::ICMP_SGT)
1521 if (Pred0 == ICmpInst::ICMP_SLT && Pred1 == ICmpInst::ICMP_SGT && isNSW)
1525 if (Pred0 == ICmpInst::ICMP_ULE && Pred1 == ICmpInst::ICMP_SGT)
1527 if (Pred0 == ICmpInst::ICMP_SLE && Pred1 == ICmpInst::ICMP_SGT && isNSW)
1533 if (Pred0 == ICmpInst::ICMP_ULT && Pred1 == ICmpInst::ICMP_UGT)
1536 if (Pred0 == ICmpInst::ICMP_ULE && Pred1 == ICmpInst::ICMP_UGT)
1653 ICmpInst::Predicate Pred0, Pred1; local
1664 if (!match(Op1, m_ICmp(Pred1, m_Specifi
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 138 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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| H A D | ARMBaseInstrInfo.cpp | 481 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, argument
483 if (Pred1.size() > 2 || Pred2.size() > 2)
486 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
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| /external/llvm/include/llvm/Target/ |
| H A D | TargetInstrInfo.h | 900 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, argument
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| /external/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 845 ICmpInst::Predicate Pred1 = (Inverted ? Cmp1->getInversePredicate() :
856 Pred1 = ICmpInst::getSwappedPredicate(Pred1);
863 switch (Pred1) {
|