Searched refs:setSubReg (Results 1 - 19 of 19) sorted by relevance

/external/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp241 MI->getOperand(0).setSubReg(KilledProdSubReg);
242 MI->getOperand(1).setSubReg(KilledProdSubReg);
243 MI->getOperand(3).setSubReg(AddSubReg);
244 MI->getOperand(2).setSubReg(OtherProdSubReg);
H A DPPCVSXCopy.cpp149 SrcMO.setSubReg(IsVRReg(DstMO.getReg(), MRI) ? PPC::sub_128 :
H A DPPCInstrInfo.cpp390 MI->getOperand(0).setSubReg(SubReg2);
394 MI->getOperand(2).setSubReg(SubReg1);
395 MI->getOperand(1).setSubReg(SubReg2);
1771 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
/external/llvm/include/llvm/CodeGen/
H A DMachineOperand.h347 void setSubReg(unsigned subReg) { function in class:llvm::MachineOperand
619 Op.setSubReg(SubReg);
/external/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp546 Copy->getOperand(0).setSubReg(SubIdx);
809 MOSrc.setSubReg(NewSubReg);
947 NewCopy->getOperand(0).setSubReg(Def.SubReg);
1011 MO.setSubReg(NewSubReg);
1141 MO.setSubReg(NewSubReg);
H A DTargetInstrInfo.cpp173 MI->getOperand(0).setSubReg(SubReg0);
177 MI->getOperand(Idx2).setSubReg(SubReg1);
178 MI->getOperand(Idx1).setSubReg(SubReg2);
H A DTwoAddressInstructionPass.cpp1436 SrcMO.setSubReg(0);
1554 MO.setSubReg(0);
1571 MO.setSubReg(0);
1703 mi->getOperand(0).setSubReg(SubIdx);
H A DVirtRegMap.cpp416 MO.setSubReg(0);
H A DLiveDebugVariables.cpp806 MO.setSubReg(locations[OldLocNo].getSubReg());
928 Loc.setSubReg(0);
H A DMachineInstr.cpp83 setSubReg(SubIdx);
92 setSubReg(0);
H A DRegAllocFast.cpp684 MO.setSubReg(0);
H A DRegisterCoalescer.cpp965 DefMO.setSubReg(0);
1001 NewMI->getOperand(0).setSubReg(NewIdx);
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp474 ImpUse.setSubReg(Defs[i].Sub);
957 Op.setSubReg(RN.Sub);
H A DHexagonBitSimplify.cpp350 I->setSubReg(NewSR);
368 I->setSubReg(NewSR);
1838 ValOp.setSubReg(H.Sub);
H A DHexagonHardwareLoops.cpp1882 MO.setSubReg(PredRSub);
H A DHexagonSplitDouble.cpp1069 Op.setSubReg(0);
/external/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp960 Src1.setSubReg(SubReg);
1102 Src0->setSubReg(Src1SubReg);
1106 Src1->setSubReg(Src2SubReg);
1912 Src0.setSubReg(Src1.getSubReg());
1917 Src1.setSubReg(Src0SubReg);
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp927 MIB->getOperand(0).setSubReg(Mips::sub_32);
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp5644 NewMI->getOperand(0).setSubReg(X86::sub_32bit);

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