/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterPressure.h | 31 LaneBitmask LaneMask; member in struct:llvm::RegisterMaskPair 33 RegisterMaskPair(unsigned RegUnit, LaneBitmask LaneMask) argument 34 : RegUnit(RegUnit), LaneMask(LaneMask) {} 247 LaneBitmask LaneMask; 249 IndexMaskPair(unsigned Index, LaneBitmask LaneMask) 250 : Index(Index), LaneMask(LaneMask) {} 282 return I->LaneMask; 285 /// Mark the \p Pair.LaneMask lane [all...] |
H A D | ScheduleDAGInstrs.h | 37 LaneBitmask LaneMask; member in struct:llvm::VReg2SUnit 40 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) argument 41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} 52 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, argument 54 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
|
H A D | MachineBasicBlock.h | 79 LaneBitmask LaneMask; member in struct:llvm::MachineBasicBlock::RegisterMaskPair 81 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask) argument 82 : PhysReg(PhysReg), LaneMask(LaneMask) {} 288 void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask = ~0u) { 289 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask)); 306 void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask = ~0u); 309 bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask = ~0u) const;
|
/external/llvm/lib/CodeGen/ |
H A D | LiveRangeEdit.cpp | 228 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); local 230 if ((S.LaneMask & LaneMask) != 0 && S.Query(Idx).isKill())
|
H A D | RegisterScavenging.cpp | 34 void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) { argument 37 if (UnitMask == 0 || (LaneMask & UnitMask) != 0) 54 setRegUsed(LI.PhysReg, LI.LaneMask);
|
H A D | RenameIndependentSubregs.cpp | 183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); local 187 if ((SR.LaneMask & LaneMask) == 0) 226 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); local 231 if ((SR.LaneMask & LaneMask) == 0) 273 SubRanges[ID-1] = Intervals[ID]->createSubRange(Allocator, SR.LaneMask);
|
H A D | VirtRegMap.cpp | 269 LaneBitmask LaneMask = 0; local 278 LaneMask |= SR->LaneMask; 280 if (LaneMask == 0) 283 MBB->addLiveIn(PhysReg, LaneMask); 344 if ((SR.LaneMask & UseMask) != 0 && SR.liveAt(BaseIndex))
|
H A D | MachineBasicBlock.cpp | 281 if (LI.LaneMask != ~0u) 282 OS << ':' << PrintLaneMask(LI.LaneMask); 325 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) { argument 332 I->LaneMask &= ~LaneMask; 333 if (I->LaneMask == 0) 337 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const { 341 return I != livein_end() && (I->LaneMask & LaneMask) != 0; 355 LaneBitmask LaneMask local [all...] |
H A D | LiveIntervalAnalysis.cpp | 524 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); local 525 if ((LaneMask & SR.LaneMask) == 0) 737 DefinedLanesMask |= SR.LaneMask; 957 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); local 959 if ((S.LaneMask & LaneMask) == 0) 961 updateRange(S, Reg, S.LaneMask); 981 void updateRange(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) { argument 988 if (LaneMask ! 1176 handleMoveUp(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) argument 1312 findLastUseBefore(SlotIndex Before, unsigned Reg, LaneBitmask LaneMask) argument 1390 repairOldRegInRange(const MachineBasicBlock::iterator Begin, const MachineBasicBlock::iterator End, const SlotIndex endIdx, LiveRange &LR, const unsigned Reg, LaneBitmask LaneMask) argument [all...] |
H A D | MachineVerifier.cpp | 217 LaneBitmask LaneMask) const; 222 void report_context_lanemask(LaneBitmask LaneMask) const; 231 LaneBitmask LaneMask = 0); 234 LaneBitmask LaneMask = 0); 249 void verifyLiveRange(const LiveRange&, unsigned, LaneBitmask LaneMask = 0); 478 LaneBitmask LaneMask) const { 481 if (LaneMask != 0) 482 report_context_lanemask(LaneMask); 509 void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const { 510 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\ 1110 checkLivenessAtUse(const MachineOperand *MO, unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit, LaneBitmask LaneMask) argument 1132 checkLivenessAtDef(const MachineOperand *MO, unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit, LaneBitmask LaneMask) argument 1581 verifyLiveRangeValue(const LiveRange &LR, const VNInfo *VNI, unsigned Reg, LaneBitmask LaneMask) argument 1673 verifyLiveRangeSegment(const LiveRange &LR, const LiveRange::const_iterator I, unsigned Reg, LaneBitmask LaneMask) argument 1871 verifyLiveRange(const LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) argument [all...] |
H A D | ScheduleDAGInstrs.cpp | 451 LaneBitmask LaneMask = I->LaneMask; local 453 if ((LaneMask & KillLaneMask) == 0) { 458 if ((LaneMask & DefLaneMask) != 0) { 468 LaneMask &= ~KillLaneMask; 470 if (LaneMask != 0) { 471 I->LaneMask = LaneMask; 489 LaneBitmask LaneMask = DefLaneMask; 493 if ((V2SU.LaneMask 536 LaneBitmask LaneMask = TrackLaneMasks ? getLaneMaskForMO(MO) : ~0u; local [all...] |
H A D | RegisterCoalescer.cpp | 93 /// A LaneMask to remember on which subregister live ranges we need to call 163 /// LaneMask are split as necessary. @p LaneMask are the lanes that 167 LaneBitmask LaneMask, CoalescerPair &CP); 172 LaneBitmask LaneMask, const CoalescerPair &CP); 814 LaneBitmask AMask = SA.LaneMask; 816 LaneBitmask BMask = SB.LaneMask; 826 SB.LaneMask = BRest; 833 SB.LaneMask = Common; 1031 SR.LaneMask 1711 const LaneBitmask LaneMask; member in class:__anon12736::JoinVals 1863 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp, LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin, bool TrackSubRegLiveness) argument 2544 joinSubRegRanges(LiveRange &LRange, LiveRange &RRange, LaneBitmask LaneMask, const CoalescerPair &CP) argument 2599 mergeSubRangeInto(LiveInterval &LI, const LiveRange &ToMerge, LaneBitmask LaneMask, CoalescerPair &CP) argument [all...] |
/external/llvm/lib/Target/X86/Utils/ |
H A D | X86ShuffleDecode.cpp | 302 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask; local 305 LaneMask += NumLanes; 307 ShuffleMask.push_back(LaneMask * NumElementsInLane + i);
|
/external/llvm/include/llvm/Target/ |
H A D | TargetRegisterInfo.h | 67 const LaneBitmask LaneMask; member in class:llvm::TargetRegisterClass 232 return LaneMask; 560 /// Transforms a LaneMask computed for one subregister to the lanemask that 578 LaneBitmask LaneMask) const { 580 return LaneMask; 581 return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask); 1119 Printable PrintLaneMask(LaneBitmask LaneMask);
|
/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.h | 62 mutable unsigned LaneMask; member in class:llvm::CodeGenSubRegIndex 113 // Compute LaneMask from Composed. Return LaneMask. 310 unsigned LaneMask; member in class:llvm::CodeGenRegisterClass 722 // LaneMask is contained in CoveringLanes will be completely covered by
|
H A D | CodeGenRegisters.cpp | 34 : TheDef(R), EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) { 45 EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) { 87 if (LaneMask) 88 return LaneMask; 91 LaneMask = ~0u; 98 LaneMask = M; 99 return LaneMask; 658 LaneMask(0) { 1178 Idx.LaneMask = 1u << Bit; 1181 Idx.LaneMask 1275 unsigned LaneMask = 0; local 1797 unsigned LaneMask = SubRegIndex->LaneMask; local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 5100 int *LaneMask = &Mask[i * ResMultiplier]; local 5105 LaneMask[j] = ExtractBase + j;
|
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 6032 int *LaneMask = &Mask[i * ResMultiplier]; local 6037 LaneMask[j] = ExtractBase + j;
|