Searched defs:RVLocs (Results 1 - 25 of 31) sorted by relevance

12

/external/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp353 SmallVector<CCValAssign, 16> RVLocs; local
357 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
371 for (unsigned i = 0; i != RVLocs.size(); ++i) {
372 CCValAssign &VA = RVLocs[i];
399 SmallVector<CCValAssign, 16> RVLocs; local
400 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
412 for (auto &Val : RVLocs) {
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
H A DBlackfinISelLowering.cpp231 SmallVector<CCValAssign, 16> RVLocs; local
235 DAG.getTarget(), RVLocs, *DAG.getContext());
243 for (unsigned i = 0; i != RVLocs.size(); ++i)
244 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
250 for (unsigned i = 0; i != RVLocs.size(); ++i) {
251 CCValAssign &VA = RVLocs[i];
382 SmallVector<CCValAssign, 16> RVLocs; local
384 DAG.getTarget(), RVLocs, *DAG.getContext());
389 for (unsigned i = 0; i != RVLocs.size(); ++i) {
390 CCValAssign &RV = RVLocs[
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp518 SmallVector<CCValAssign, 16> RVLocs; local
520 getTargetMachine(), RVLocs, *DAG.getContext());
525 for (unsigned i = 0; i != RVLocs.size(); ++i) {
526 CCValAssign &VA = RVLocs[i];
561 SmallVector<CCValAssign, 16> RVLocs; local
565 getTargetMachine(), RVLocs, *DAG.getContext());
573 for (unsigned i = 0; i != RVLocs.size(); ++i)
574 if (RVLocs[i].isRegLoc())
575 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
581 for (unsigned i = 0; i != RVLocs
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/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp352 SmallVectorImpl<CCValAssign> &RVLocs,
358 std::reverse(RVLocs.begin(), RVLocs.end());
512 SmallVector<CCValAssign, 16> RVLocs; local
519 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
523 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
529 for (unsigned i = 0; i != RVLocs.size(); ++i) {
530 CCValAssign &VA = RVLocs[i];
697 SmallVector<CCValAssign, 16> RVLocs; local
698 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
351 AnalyzeReturnValues(CCState &State, SmallVectorImpl<CCValAssign> &RVLocs, const SmallVectorImpl<ArgT> &Args) argument
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
H A DAlphaISelLowering.cpp355 SmallVector<CCValAssign, 16> RVLocs; local
357 getTargetMachine(), RVLocs, *DAG.getContext());
362 for (unsigned i = 0; i != RVLocs.size(); ++i) {
363 CCValAssign &VA = RVLocs[i];
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
H A DMBlazeISelLowering.cpp841 SmallVector<CCValAssign, 16> RVLocs; local
843 getTargetMachine(), RVLocs, *DAG.getContext());
848 for (unsigned i = 0; i != RVLocs.size(); ++i) {
849 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
850 RVLocs[i].getValVT(), InFlag).getValue(1);
1014 SmallVector<CCValAssign, 16> RVLocs; local
1018 getTargetMachine(), RVLocs, *DAG.getContext());
1026 for (unsigned i = 0; i != RVLocs.size(); ++i)
1027 if (RVLocs[i].isRegLoc())
1028 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp390 SmallVector<CCValAssign, 16> RVLocs; local
400 getTargetMachine(), RVLocs, *DAG.getContext());
408 for (unsigned i = 0; i != RVLocs.size(); ++i)
409 if (RVLocs[i].isRegLoc())
410 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
416 for (unsigned i = 0; i != RVLocs.size(); ++i) {
417 CCValAssign &VA = RVLocs[i];
575 SmallVector<CCValAssign, 16> RVLocs; local
577 getTargetMachine(), RVLocs, *DAG.getContext());
582 for (unsigned i = 0; i != RVLocs
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
H A DSparcISelLowering.cpp90 SmallVector<CCValAssign, 16> RVLocs; local
94 DAG.getTarget(), RVLocs, *DAG.getContext());
102 for (unsigned i = 0; i != RVLocs.size(); ++i)
103 if (RVLocs[i].isRegLoc())
104 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
110 for (unsigned i = 0; i != RVLocs.size(); ++i) {
111 CCValAssign &VA = RVLocs[i];
592 SmallVector<CCValAssign, 16> RVLocs; local
594 DAG.getTarget(), RVLocs, *DAG.getContext());
599 for (unsigned i = 0; i != RVLocs
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/external/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp525 SmallVector<CCValAssign, 16> RVLocs; local
528 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
538 for (unsigned i = 0; i != RVLocs.size(); ++i) {
539 CCValAssign &VA = RVLocs[i];
767 SmallVector<CCValAssign, 16> RVLocs; local
768 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
774 for (unsigned I = 0; I != RVLocs.size(); ++I) {
775 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
776 RVLocs[I].getValVT(), InFlag)
/external/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1225 SmallVector<CCValAssign, 16> RVLocs; local
1226 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1230 if (RVLocs.size() != 1)
1233 MVT CopyVT = RVLocs[0].getValVT();
1243 ResultReg).addReg(RVLocs[0].getLocReg());
1244 CLI.InRegs.push_back(RVLocs[0].getLocReg());
H A DMipsISelLowering.cpp2904 SmallVector<CCValAssign, 16> RVLocs; local
2905 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2910 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2911 CCValAssign &VA = RVLocs[i];
2914 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2915 RVLocs[i].getLocVT(), InFlag);
3181 SmallVector<CCValAssign, 16> RVLocs; local
3182 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3216 SmallVector<CCValAssign, 16> RVLocs; local
3220 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DA
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/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1405 SmallVector<CCValAssign, 16> RVLocs; local
1406 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1408 CCValAssign &VA = RVLocs[0];
1409 assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1494 SmallVector<CCValAssign, 16> RVLocs; local
1495 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1497 if (RVLocs.size() > 1)
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1071 const SmallVectorImpl<CCValAssign> &RVLocs,
1076 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1077 const CCValAssign &VA = RVLocs[i];
1134 SmallVector<CCValAssign, 16> RVLocs; local
1136 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1239 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals);
1438 SmallVector<CCValAssign, 16> RVLocs; local
1439 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1460 SmallVector<CCValAssign, 16> RVLocs; local
1463 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1070 LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl<CCValAssign> &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMFastISel.cpp1679 SmallVector<CCValAssign, 16> RVLocs; local
1680 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1684 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1687 EVT DestVT = RVLocs[0].getValVT();
1692 .addReg(RVLocs[0].getLocReg())
1693 .addReg(RVLocs[1].getLocReg()));
1695 UsedRegs.push_back(RVLocs[0].getLocReg());
1696 UsedRegs.push_back(RVLocs[1].getLocReg());
1701 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1702 EVT CopyVT = RVLocs[
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86FastISel.cpp1867 SmallVector<CCValAssign, 16> RVLocs; local
1868 CCState CCRetInfo(CC, false, *FuncInfo.MF, TM, RVLocs,
1872 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1873 EVT CopyVT = RVLocs[i].getValVT();
1879 if ((RVLocs[i].getLocReg() == X86::ST0 ||
1880 RVLocs[i].getLocReg() == X86::ST1)) {
1881 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
1889 CopyReg).addReg(RVLocs[i].getLocReg());
1890 UsedRegs.push_back(RVLocs[i].getLocReg());
1893 if (CopyVT != RVLocs[
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
H A DXCoreISelLowering.cpp1028 SmallVector<CCValAssign, 16> RVLocs; local
1030 getTargetMachine(), RVLocs, *DAG.getContext());
1035 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1036 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1037 RVLocs[i].getValVT(), InFlag).getValue(1);
1198 SmallVector<CCValAssign, 16> RVLocs; local
1199 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
1212 SmallVector<CCValAssign, 16> RVLocs; local
1216 getTargetMachine(), RVLocs, *DAG.getContext());
1224 for (unsigned i = 0; i != RVLocs
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/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp2027 SmallVector<CCValAssign, 16> RVLocs; local
2028 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2032 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2035 MVT DestVT = RVLocs[0].getValVT();
2040 .addReg(RVLocs[0].getLocReg())
2041 .addReg(RVLocs[1].getLocReg()));
2043 UsedRegs.push_back(RVLocs[0].getLocReg());
2044 UsedRegs.push_back(RVLocs[1].getLocReg());
2049 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2050 MVT CopyVT = RVLocs[
2200 SmallVector<CCValAssign, 16> RVLocs; local
2310 SmallVector<CCValAssign, 16> RVLocs; local
[all...]
/external/llvm/lib/Target/X86/
H A DX86FastISel.cpp3346 SmallVector<CCValAssign, 16> RVLocs; local
3347 CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs,
3353 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3354 CCValAssign &VA = RVLocs[i];
3395 CLI.NumResultRegs = RVLocs.size();
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
H A DSPUISelLowering.cpp1434 SmallVector<CCValAssign, 16> RVLocs;
1436 getTargetMachine(), RVLocs, *DAG.getContext());
1441 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1442 CCValAssign VA = RVLocs[i];
1461 SmallVector<CCValAssign, 16> RVLocs; local
1463 getTargetMachine(), RVLocs, *DAG.getContext());
1469 for (unsigned i = 0; i != RVLocs.size(); ++i)
1470 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1476 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1477 CCValAssign &VA = RVLocs[
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
H A DMipsISelLowering.cpp2196 SmallVector<CCValAssign, 16> RVLocs; local
2198 getTargetMachine(), RVLocs, *DAG.getContext());
2203 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2204 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
2205 RVLocs[i].getValVT(), InFlag).getValue(1);
2426 SmallVector<CCValAssign, 16> RVLocs; local
2430 getTargetMachine(), RVLocs, *DAG.getContext());
2438 for (unsigned i = 0; i != RVLocs.size(); ++i)
2439 if (RVLocs[i].isRegLoc())
2440 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3032 SmallVector<CCValAssign, 16> RVLocs; local
3033 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
3037 if (RVLocs.size() != 1)
3041 MVT CopyVT = RVLocs[0].getValVT();
3050 .addReg(RVLocs[0].getLocReg());
3051 CLI.InRegs.push_back(RVLocs[0].getLocReg());
/external/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp983 SmallVector<CCValAssign, 48> RVLocs; local
986 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
998 i != RVLocs.size();
1000 CCValAssign &VA = RVLocs[i];
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp563 SmallVector<CCValAssign, 16> RVLocs; local
566 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
576 for (unsigned i = 0; i != RVLocs.size(); ++i) {
577 CCValAssign &VA = RVLocs[i];
616 SmallVector<CCValAssign, 16> RVLocs; local
618 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
624 for (unsigned i = 0; i != RVLocs.size(); ++i) {
626 if (RVLocs[i].getValVT() == MVT::i1) {
633 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
643 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp214 SmallVector<CCValAssign, 16> RVLocs; local
217 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
230 i != RVLocs.size();
232 CCValAssign &VA = RVLocs[i];
252 VA = RVLocs[++i]; // skip ahead to next loc
297 SmallVector<CCValAssign, 16> RVLocs; local
300 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
314 for (unsigned i = 0; i != RVLocs.size(); ++i) {
315 CCValAssign &VA = RVLocs[i];
343 if (i+1 < RVLocs
992 SmallVector<CCValAssign, 16> RVLocs; local
1350 SmallVector<CCValAssign, 16> RVLocs; local
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
H A DPPCISelLowering.cpp2711 SmallVector<CCValAssign, 16> RVLocs; local
2713 getTargetMachine(), RVLocs, *DAG.getContext());
2717 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2718 CCValAssign &VA = RVLocs[i];
2761 SmallVector<CCValAssign, 16> RVLocs; local
2763 getTargetMachine(), RVLocs, *DAG.getContext());
2765 for (unsigned i = 0; i != RVLocs.size(); ++i)
2766 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3424 SmallVector<CCValAssign, 16> RVLocs; local
3426 RVLocs, Contex
3437 SmallVector<CCValAssign, 16> RVLocs; local
[all...]

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