/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) argument 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 42 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 43 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 44 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 46 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 48 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 50 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 52 bool isPTR64() const { return STI 508 createMipsDisassembler( const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument 515 createMipselDisassembler( const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument [all...] |
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsTargetStreamer.cpp | 102 const MCSubtargetInfo *STI) { 130 const MCSubtargetInfo *STI) { 135 getStreamer().EmitInstruction(TmpInst, *STI); 139 SMLoc IDLoc, const MCSubtargetInfo *STI) { 145 getStreamer().EmitInstruction(TmpInst, *STI); 149 SMLoc IDLoc, const MCSubtargetInfo *STI) { 150 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); 154 SMLoc IDLoc, const MCSubtargetInfo *STI) { 155 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); 159 SMLoc IDLoc, const MCSubtargetInfo *STI) { 100 emitDirectiveCpRestore( int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 129 emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 138 emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 148 emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 153 emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 158 emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 168 emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 180 emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 186 emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 192 emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit, const MCSubtargetInfo *STI) argument 199 emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 210 emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 218 emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) argument 223 emitGPRestore(int Offset, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 230 emitStoreWithImmOffset( unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 265 emitStoreWithSymOffset( unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand, MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 284 emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg, int64_t Offset, unsigned TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 321 emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg, MCOperand &HiOperand, MCOperand &LoOperand, unsigned TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 588 emitDirectiveCpRestore( int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) argument 659 MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI) argument 1051 emitDirectiveCpRestore( int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) argument [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 688 const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM); 690 bool IsABICalls = STI.isABICalls(); 710 STI.isNaN2008() ? TS.emitDirectiveNaN2008() 715 TS.updateABIInfo(STI); 720 if (ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit())) 726 if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX())) 752 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) { argument 757 OutStreamer->EmitInstruction(I, STI); 760 EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg) argument 768 EmitInstrRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2) argument 788 EmitInstrRegRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2, unsigned Reg3) argument 799 EmitMovFPIntPair(const MCSubtargetInfo &STI, unsigned MovOpc, unsigned Reg1, unsigned Reg2, unsigned FPReg1, unsigned FPReg2, bool LE) argument 812 EmitSwapFPIntParams(const MCSubtargetInfo &STI, Mips16HardFloatInfo::FPParamVariant PV, bool LE, bool ToFP) argument 844 EmitSwapFPIntRetval( const MCSubtargetInfo &STI, Mips16HardFloatInfo::FPReturnVariant RV, bool LE) argument [all...] |
H A D | MipsConstantIslandPass.cpp | 335 const MipsSubtarget *STI; member in class:__anon13195::MipsConstantIslands 356 : MachineFunctionPass(ID), STI(nullptr), MF(nullptr), MCP(nullptr), 442 STI = &static_cast<const MipsSubtarget &>(mf.getSubtarget()); 444 if (!STI->inMips16Mode() || !MipsSubtarget::useConstantIslands()) { 447 TII = (const Mips16InstrInfo *)STI->getInstrInfo();
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 110 const NVPTXSubtarget &STI) 111 : TargetLowering(TM), nvTM(&TM), STI(STI) { 174 if (STI.hasROT64()) { 181 if (STI.hasROT32()) { 284 computeRegisterProperties(STI.getRegisterInfo()); 906 bool isABI = (STI.getSmVersion() >= 20); 1068 bool isABI = (STI.getSmVersion() >= 20); 1495 assert(STI.getTargetLowering()->getNumRegisters(F->getContext(), 1716 if (VTBits == 32 && STI 109 NVPTXTargetLowering(const NVPTXTargetMachine &TM, const NVPTXSubtarget &STI) argument [all...] |
H A D | NVPTXAsmPrinter.cpp | 822 const NVPTXSubtarget STI(TT, CPU, FS, NTM); 854 emitHeader(M, OS1, STI); 912 const NVPTXSubtarget &STI) { 918 unsigned PTXVersion = STI.getPTXVersion(); 922 O << STI.getTargetName(); 928 if (!STI.hasDouble()) 911 emitHeader(Module &M, raw_ostream &O, const NVPTXSubtarget &STI) argument
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCAsmPrinter.cpp | 1302 const PPCSubtarget &STI = TM.getSubtarget<PPCSubtarget>(F); local 1303 unsigned FDir = STI.getDarwinDirective(); 1304 Directive = Directive > FDir ? FDir : STI.getDarwinDirective(); 1305 if (STI.hasMFOCRF() && Directive < PPC::DIR_970) 1307 if (STI.hasAltivec() && Directive < PPC::DIR_7400) 1309 if (STI.isPPC64() && Directive < PPC::DIR_64)
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H A D | PPCFrameLowering.cpp | 40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) { argument 41 if (STI.isDarwinABI()) 42 return STI.isPPC64() ? 16 : 8; 44 return STI.isPPC64() ? 16 : 4; 47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) { argument 48 return STI.isELFv2ABI() ? 24 : 40; 51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) { argument 57 if (STI.isDarwinABI()) 58 return STI.isPPC64() ? -8U : -4U; 61 return STI 64 computeLinkageSize(const PPCSubtarget &STI) argument 72 computeBasePointerSaveOffset(const PPCSubtarget &STI) argument 82 PPCFrameLowering(const PPCSubtarget &STI) argument [all...] |
/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 44 bool is64BitMode(const MCSubtargetInfo &STI) const { 45 return STI.getFeatureBits()[X86::Mode64Bit]; 48 bool is32BitMode(const MCSubtargetInfo &STI) const { 49 return STI.getFeatureBits()[X86::Mode32Bit]; 52 bool is16BitMode(const MCSubtargetInfo &STI) const { 53 return STI.getFeatureBits()[X86::Mode16Bit]; 59 const MCSubtargetInfo &STI) const { 64 if (is16BitMode(STI) && BaseReg.getReg() == 0 && 128 const MCSubtargetInfo &STI) const; 132 const MCSubtargetInfo &STI) cons 1057 emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, const MCInstrDesc &Desc, const MCSubtargetInfo &STI, raw_ostream &OS) const argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 80 const MCSubtargetInfo &STI); 83 const MCSubtargetInfo &STI, 89 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI); 97 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) { 101 MF->getSubtarget<X86Subtarget>().is64Bit(), STI); 774 const MCSubtargetInfo &STI) { 813 OS.EmitInstruction(MCInstBuilder(Opc), STI); local 816 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI); local 826 STI); local 835 const MCSubtargetInfo &STI) { 82 count(MCInst &Inst, const MCSubtargetInfo &STI, MCCodeEmitter *CodeEmitter) argument 96 emitShadowPadding( MCStreamer &OutStreamer, const MCSubtargetInfo &STI) argument 773 EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) argument 834 EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) argument [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/Support/ |
H A D | TargetRegistry.h | 95 typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI, 98 const MCSubtargetInfo &STI); 102 const MCSubtargetInfo &STI); 104 const MCSubtargetInfo &STI, 363 MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI, argument 367 return MCAsmParserCtorFn(STI, Parser); 378 MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI) const { 381 return MCDisassemblerCtorFn(*this, STI); 386 const MCSubtargetInfo &STI) const { 389 return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, STI); 394 createMCCodeEmitter(const MCInstrInfo &II, const MCSubtargetInfo &STI, MCContext &Ctx) const argument 1075 Allocator(MCSubtargetInfo &STI, MCAsmParser &P) argument 1115 Allocator(const MCInstrInfo &II, const MCSubtargetInfo &STI, MCContext &Ctx) argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 40 const MCSubtargetInfo &STI; member in class:__anon20032::ARMMCCodeEmitter 45 : MCII(mcii), STI(sti) { 52 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 55 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0; 58 Triple TT(STI.getTargetTriple()); 338 const MCSubtargetInfo &STI, 340 return new ARMMCCodeEmitter(MCII, STI, Ctx); 337 createARMMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 36 MCSubtargetInfo &STI; member in class:__anon20122::X86ATTAsmParser 66 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; 69 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit)); 83 : MCTargetAsmParser(), STI(sti), Parser(parser) { 86 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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/external/llvm/lib/CodeGen/ |
H A D | TargetInstrInfo.cpp | 954 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, argument
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/external/llvm/lib/MC/ |
H A D | MCStreamer.cpp | 691 const MCInst &Inst, const MCSubtargetInfo &STI) { 692 InstPrinter.printInst(&Inst, OS, "", STI); 725 const MCSubtargetInfo &STI) { 690 prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS, const MCInst &Inst, const MCSubtargetInfo &STI) argument 724 EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 34 const R600Subtarget &STI) 35 : AMDGPUTargetLowering(TM, STI), Gen(STI.getGeneration()) { 43 computeRegisterProperties(STI.getRegisterInfo()); 33 R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI) argument
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/external/llvm/lib/Target/ARM/ |
H A D | ARMConstantIslandPass.cpp | 271 const ARMSubtarget *STI; member in class:__anon13018::ARMConstantIslands 406 STI = &static_cast<const ARMSubtarget &>(MF->getSubtarget()); 407 TII = STI->getInstrInfo(); 495 if (isThumb2 && !STI->prefers32BitThumb()) 499 if (isThumb && STI->hasV8MBaselineOps())
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/external/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 45 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, argument 47 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} 144 const MCSubtargetInfo &STI, 146 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 176 HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo()); 318 decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI); 143 createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 59 const LanaiSubtarget &STI) 65 TRI = STI.getRegisterInfo(); 58 LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI) argument
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/external/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 291 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &, argument 293 : MCTargetAsmParser(Options, STI), MII(MII) { 295 const Triple &TheTriple = STI.getTargetTriple(); 300 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 85 const SystemZSubtarget &STI) 86 : TargetLowering(TM), Subtarget(STI) { 84 SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI) argument
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 85 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) argument 87 Subtarget(STI) {
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H A D | ARMConstantIslandPass.cpp | 169 const ARMSubtarget *STI; member in class:__anon19990::ARMConstantIslands 277 STI = &MF.getTarget().getSubtarget<ARMSubtarget>(); 360 if (isThumb2 && !STI->prefers32BitThumb())
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H A D | ARMLoadStoreOptimizer.cpp | 1412 const ARMSubtarget *STI; member in struct:__anon20000::ARMPreAllocLoadStoreOpt 1442 STI = &Fn.getTarget().getSubtarget<ARMSubtarget>(); 1510 if (!STI->hasV5TEOps()) 1539 unsigned ReqAlign = STI->hasV6Ops()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 39 ARMDisassembler(const MCSubtargetInfo &STI) : argument 40 MCDisassembler(STI) { 64 ThumbDisassembler(const MCSubtargetInfo &STI) : argument 65 MCDisassembler(STI) { 322 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { argument 323 return new ARMDisassembler(STI); 326 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { argument 327 return new ThumbDisassembler(STI); 347 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 363 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); [all...] |