| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCEarlyReturn.cpp | 65 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
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| H A D | PPCInstrInfo.cpp | 1329 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1489 case PPC::BLR:
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| H A D | PPCFrameLowering.cpp | 1311 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64AsmPrinter.cpp | 411 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
555 Blr.setOpcode(AArch64::BLR);
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| H A D | AArch64FastISel.cpp | 3128 const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
3161 const MCInstrDesc &II = TII.get(AArch64::BLR);
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| /external/v8/src/arm64/ |
| H A D | instructions-arm64.h | 335 return Mask(UnconditionalBranchToRegisterMask) == BLR;
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| H A D | disasm-arm64.cc | 543 case BLR: mnemonic = "blr"; break;
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| H A D | assembler-arm64-inl.h | 562 Emit(BLR | Rn(xzr));
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| H A D | constants-arm64.h | 612 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, enumerator in enum:v8::internal::UnconditionalBranchToRegisterOp
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| H A D | assembler-arm64.cc | 959 Emit(BLR | Rn(xzr));
988 Emit(BLR | Rn(xn));
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| H A D | simulator-arm64.cc | 1371 case BLR: {
1374 // BLR XZR is used as a guard for the constant pool. We should never hit
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| H A D | RegisterCoalescer.cpp | 430 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); local
431 if (BLR == IntB.end()) return false;
432 VNInfo *BValNo = BLR->valno;
489 if (ValLR+1 != BLR) return false;
510 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
518 // [ValLR.end, BLR.begin) of either value number, then we merge the
727 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
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| /external/selinux/mcstrans/share/examples/nato/setrans.d/ |
| H A D | eyes-only.conf | 97 ~c228=BLR # Belarus
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| H A D | rel.conf | 103 ~c200,~c228=BLR # Belarus
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| /external/pcre/dist2/src/sljit/ |
| H A D | sljitNativeARM_64.c | 74 #define BLR 0xd63f0000 macro
1901 PTR_FAIL_IF(push_inst(compiler, ((type >= SLJIT_FAST_CALL) ? BLR : BR) | RN(TMP_REG1)));
1954 return push_inst(compiler, ((type >= SLJIT_FAST_CALL) ? BLR : BR) | RN(src));
1964 return push_inst(compiler, ((type >= SLJIT_FAST_CALL) ? BLR : BR) | RN(TMP_REG1));
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| H A D | sljitNativePPC_common.c | 149 #define BLR (HI(19) | LO(16) | (0x14 << 21)) macro
695 FAIL_IF(push_inst(compiler, BLR));
2049 return push_inst(compiler, BLR);
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 513 assert((RetOpcode == PPC::BLR ||
658 if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
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| /external/vixl/src/aarch64/ |
| H A D | constants-aarch64.h | 652 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, enumerator in enum:vixl::aarch64::UnconditionalBranchToRegisterOp
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| H A D | disasm-aarch64.cc | 613 case BLR:
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| H A D | simulator-aarch64.cc | 1024 case BLR:
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| H A D | assembler-aarch64.cc | 188 Emit(BLR | Rn(xn));
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| /external/capstone/arch/PowerPC/ |
| H A D | PPCGenAsmWriter.inc | 215 9472U, // BLR
1488 0U, // BLR
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| /external/capstone/arch/AArch64/ |
| H A D | AArch64GenAsmWriter.inc | 140 2107319U, // BLR
2532 0U, // BLR
5583 // BLR, BR, CLREX, RET, TLSDESCCALL
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