| /external/v8/src/compiler/arm64/ |
| H A D | code-generator-arm64.cc | 1275 __ Cmn(i.InputOrZeroRegister64(0), i.InputOperand2_64(1));
1278 __ Cmn(i.InputOrZeroRegister32(0), i.InputOperand2_32(1));
1397 __ Cmn(i.OutputRegister32(), 1);
1408 __ Cmn(i.OutputRegister32(), 1);
|
| /external/vixl/test/aarch32/ |
| H A D | test-simulator-cond-rd-operand-const-a32.cc | 116 M(Cmn) \
|
| H A D | test-simulator-cond-rd-operand-const-t32.cc | 116 M(Cmn) \
|
| H A D | test-disasm-a32.cc | 2347 TEST_SHIFT_T32(Cmn, "cmn", 0x0000000a)
2369 TEST_WIDE_IMMEDIATE(Cmn, "cmn", 0x0000000e);
2372 TEST_WIDE_IMMEDIATE_PC(Cmn, "cmn", 0x0000000e);
3307 COMPARE_T32(Cmn(eq, r0, r1),
3311 COMPARE_T32(Cmn(eq, r0, r8),
|
| H A D | test-simulator-cond-rd-operand-rn-a32.cc | 116 M(Cmn) \
|
| H A D | test-simulator-cond-rd-operand-rn-t32.cc | 116 M(Cmn) \
|
| H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 116 M(Cmn) \
|
| H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 116 M(Cmn) \
|
| H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 116 M(Cmn) \
|
| H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 116 M(Cmn) \
|
| H A D | test-simulator-cond-rd-operand-rn-shift-rs-a32.cc | 116 M(Cmn) \
|
| /external/v8/src/regexp/arm64/ |
| H A D | regexp-macro-assembler-arm64.cc | 306 __ Cmn(capture_length, current_input_offset());
467 __ Cmn(capture_length, current_input_offset());
|
| /external/swiftshader/third_party/subzero/src/ |
| H A D | IceInstARM32.h | 389 Cmn, enumerator in enum:Ice::ARM32::InstARM32::InstKindARM32
1066 using InstARM32Cmn = InstARM32CmpLike<InstARM32::Cmn>;
|
| H A D | IceInstARM32.cpp | 3537 template class InstARM32CmpLike<InstARM32::Cmn>;
|
| /external/v8/src/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 202 void MacroAssembler::Cmn(const Register& rn, const Operand& operand) { function in class:v8::internal::MacroAssembler
|
| H A D | macro-assembler-arm64.h | 217 inline void Cmn(const Register& rn, const Operand& operand);
|
| /external/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.cc | 1446 void MacroAssembler::Cmn(const Register& rn, const Operand& operand) { function in class:vixl::aarch64::MacroAssembler
|
| H A D | macro-assembler-aarch64.h | 673 void Cmn(const Register& rn, const Operand& operand);
|
| /external/vixl/test/aarch64/ |
| H A D | test-disasm-aarch64.cc | 2972 COMPARE_MACRO(Cmn(w0, -1), "cmp w0, #0x1 (1)");
2973 COMPARE_MACRO(Cmn(x1, -1), "cmp x1, #0x1 (1)");
2974 COMPARE_MACRO(Cmn(w2, -4095), "cmp w2, #0xfff (4095)");
2975 COMPARE_MACRO(Cmn(x3, -4095), "cmp x3, #0xfff (4095)");
|
| H A D | test-assembler-aarch64.cc | 8985 __ Cmn(x1, Operand(x0));
8995 __ Cmn(w1, Operand(w0));
9005 __ Cmn(x1, Operand(x0));
9015 __ Cmn(w1, Operand(w0));
13325 __ Cmn(w1, w1); // Set N and V.
13327 // The Msr should have overwritten every flag set by the Cmn.
|
| /external/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 1562 void Cmn(Condition cond, Register rn, const Operand& operand) { function in class:vixl::aarch32::MacroAssembler
1575 void Cmn(Register rn, const Operand& operand) { Cmn(al, rn, operand); } function in class:vixl::aarch32::MacroAssembler
|