Searched refs:HasBaseReg (Results 1 - 25 of 28) sorted by relevance

12

/external/swiftshader/third_party/LLVM/include/llvm/Transforms/Utils/
H A DAddrModeMatcher.h46 (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale);
/external/swiftshader/third_party/LLVM/lib/Transforms/Utils/
H A DAddrModeMatcher.cpp269 if (AddrMode.HasBaseReg) {
274 AddrMode.HasBaseReg = true;
285 if (AddrMode.HasBaseReg)
287 AddrMode.HasBaseReg = true;
354 if (!AddrMode.HasBaseReg) {
355 AddrMode.HasBaseReg = true;
360 AddrMode.HasBaseReg = false;
/external/llvm/include/llvm/Analysis/
H A DTargetTransformInfoImpl.h205 bool HasBaseReg, int64_t Scale,
221 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) {
223 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
446 bool HasBaseReg = (BaseGV == nullptr); local
483 BaseOffset, HasBaseReg, Scale, AS)) {
204 isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) argument
220 getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) argument
H A DTargetTransformInfo.h330 bool HasBaseReg, int64_t Scale,
351 bool HasBaseReg, int64_t Scale,
652 int64_t BaseOffset, bool HasBaseReg,
660 int64_t BaseOffset, bool HasBaseReg,
800 bool HasBaseReg, int64_t Scale,
802 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
818 bool HasBaseReg, int64_t Scale,
820 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
/external/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp119 bool HasBaseReg,
122 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
144 bool HasBaseReg,
147 int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
117 isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const argument
142 getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const argument
/external/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp236 bool HasBaseReg = BaseReg.getReg() != 0; local
237 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") &&
239 HasBaseReg = false;
242 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
266 if (HasBaseReg)
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86AsmPrinter.cpp287 bool HasBaseReg = BaseReg.getReg() != 0; local
288 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") &&
290 HasBaseReg = false;
293 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
313 if (HasBaseReg)
/external/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp253 bool HasBaseReg; member in struct:__anon14730::Formula
280 : BaseGV(nullptr), BaseOffset(0), HasBaseReg(false), Scale(0),
369 HasBaseReg = true;
375 HasBaseReg = true;
480 if (HasBaseReg && BaseRegs.empty()) {
482 OS << "**error: HasBaseReg**";
483 } else if (!HasBaseReg && !BaseRegs.empty()) {
485 OS << "**error: !HasBaseReg**";
1359 bool HasBaseReg, int64_t Scale) {
1363 HasBaseReg, Scal
1356 isAMCompletelyFolded(const TargetTransformInfo &TTI, LSRUse::KindType Kind, MemAccessTy AccessTy, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale) argument
1408 isAMCompletelyFolded(const TargetTransformInfo &TTI, int64_t MinOffset, int64_t MaxOffset, LSRUse::KindType Kind, MemAccessTy AccessTy, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale) argument
1446 isLegalUse(const TargetTransformInfo &TTI, int64_t MinOffset, int64_t MaxOffset, LSRUse::KindType Kind, MemAccessTy AccessTy, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale) argument
1510 isAlwaysFoldable(const TargetTransformInfo &TTI, LSRUse::KindType Kind, MemAccessTy AccessTy, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg) argument
1532 isAlwaysFoldable(const TargetTransformInfo &TTI, ScalarEvolution &SE, int64_t MinOffset, int64_t MaxOffset, LSRUse::KindType Kind, MemAccessTy AccessTy, const SCEV *S, bool HasBaseReg) argument
2206 reconcileNewOffset(LSRUse &LU, int64_t NewOffset, bool HasBaseReg, LSRUse::KindType Kind, MemAccessTy AccessTy) argument
[all...]
/external/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h127 bool HasBaseReg, int64_t Scale,
132 AM.HasBaseReg = HasBaseReg;
138 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) {
142 AM.HasBaseReg = HasBaseReg;
126 isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) argument
137 getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) argument
/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp220 /// non-empty, AM.HasBaseReg should be set to true.
318 AM.HasBaseReg = true;
324 AM.HasBaseReg = true;
386 if (AM.HasBaseReg && BaseRegs.empty()) {
388 OS << "**error: HasBaseReg**";
389 } else if (!AM.HasBaseReg && !BaseRegs.empty()) {
391 OS << "**error: !HasBaseReg**";
1197 if (AM.Scale != 0 && AM.HasBaseReg && AM.BaseOffs != 0)
1249 bool HasBaseReg,
1260 AM.HasBaseReg
1247 isAlwaysFoldable(int64_t BaseOffs, GlobalValue *BaseGV, bool HasBaseReg, LSRUse::KindType Kind, Type *AccessTy, const TargetLowering *TLI) argument
1273 isAlwaysFoldable(const SCEV *S, int64_t MinOffset, int64_t MaxOffset, bool HasBaseReg, LSRUse::KindType Kind, Type *AccessTy, const TargetLowering *TLI, ScalarEvolution &SE) argument
1898 reconcileNewOffset(LSRUse &LU, int64_t NewOffset, bool HasBaseReg, LSRUse::KindType Kind, Type *AccessTy) argument
[all...]
/external/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp2093 (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale);
3285 if (AddrMode.HasBaseReg) {
3290 AddrMode.HasBaseReg = true;
3301 if (AddrMode.HasBaseReg)
3303 AddrMode.HasBaseReg = true;
3436 if (!AddrMode.HasBaseReg) {
3437 AddrMode.HasBaseReg = true;
3442 AddrMode.HasBaseReg = false;
H A DTargetLoweringBase.cpp1792 case 0: // "r+i" or just "i", depending on HasBaseReg.
1795 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1800 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
/external/swiftshader/third_party/LLVM/include/llvm/Target/
H A DTargetLowering.h1522 /// If HasBaseReg is false, there is no base register.
1529 bool HasBaseReg;
1531 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
/external/llvm/include/llvm/Target/
H A DTargetLowering.h1587 /// If HasBaseReg is false, there is no base register.
1593 bool HasBaseReg;
1595 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
/external/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp315 case 0: // r + i or just i, depending on HasBaseReg.
320 if (AM.HasBaseReg) {
386 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
389 if (AM.Scale == 1 && AM.HasBaseReg)
407 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
410 if (AM.Scale == 1 && AM.HasBaseReg)
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
H A DSPUISelLowering.cpp3251 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && AM.BaseOffs == 0)
3255 if (AM.BaseGV ==0 && AM.HasBaseReg && AM.Scale == 0 && isInt<14>(AM.BaseOffs))
3259 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 1 && AM.BaseOffs ==0)
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp3198 case 0: // "r+i" or just "i", depending on HasBaseReg.
3201 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3206 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1914 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
H A DXCoreISelLowering.cpp1565 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp3738 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale;
3745 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
H A DPPCISelLowering.cpp5675 case 0: // "r+i" or just "i", depending on HasBaseReg.
5678 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5683 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp3671 case 0: // "r+i" or just "i", depending on HasBaseReg.
3674 if (!AM.HasBaseReg) // allow "r+i".
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp11349 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
11408 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp11572 case 0: // "r+i" or just "i", depending on HasBaseReg.
11575 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
11580 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMISelLowering.cpp8120 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
8178 if (((unsigned)AM.HasBaseReg + Scale) <= 2)

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