/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 255 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 258 INSERT_VECTOR_ELT, enumerator in enum:llvm::ISD::NodeType
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetTransformInfo.cpp | 339 if (ISD == ISD::INSERT_VECTOR_ELT) 347 ISD == ISD::INSERT_VECTOR_ELT)
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 271 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 274 INSERT_VECTOR_ELT, enumerator in enum:llvm::ISD::NodeType
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypesGeneric.cpp | 446 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); 450 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx);
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H A D | LegalizeVectorTypes.cpp | 59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 602 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 989 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 993 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 2064 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 2302 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx], 2832 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), 3481 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
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H A D | SelectionDAGDumper.cpp | 218 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
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H A D | LegalizeIntegerTypes.cpp | 96 case ISD::INSERT_VECTOR_ELT: 892 case ISD::INSERT_VECTOR_ELT: 2753 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 3388 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
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H A D | LegalizeDAG.cpp | 93 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 310 /// INSERT_VECTOR_ELT instruction. In this case, it 2988 case ISD::INSERT_VECTOR_ELT: 4001 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) { 4316 case ISD::INSERT_VECTOR_ELT: { 4359 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
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/external/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 171 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); 172 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); 173 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 174 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 199 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 618 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 910 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), 1996 case ISD::INSERT_VECTOR_ELT: {
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H A D | SIISelLowering.cpp | 147 case ISD::INSERT_VECTOR_ELT: 171 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); 172 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypesGeneric.cpp | 364 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); 367 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx);
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H A D | LegalizeVectorTypes.cpp | 58 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 429 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 654 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 657 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 1238 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 1418 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, 1872 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(), 2254 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
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H A D | LegalizeIntegerTypes.cpp | 83 case ISD::INSERT_VECTOR_ELT: 766 case ISD::INSERT_VECTOR_ELT: 2431 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 2978 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 121 /// lowering INSERT_VECTOR_ELT operations easier. 701 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 871 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 875 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 941 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 942 setOperationAction(ISD::INSERT_VECTOR_ELT, MV [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 101 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 626 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 1490 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1504 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 3287 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 3290 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 5763 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT), 5782 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops); 5833 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we 5846 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, d [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1954 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, 1980 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom); 2493 // When there are non constant operands, add them with INSERT_VECTOR_ELT to 2678 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ? 2772 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 257 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 306 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 1941 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 2344 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT. 2403 // Use INSERT_VECTOR_ELT operations rather than expand to stores. 2413 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 1311 case ISD::INSERT_VECTOR_ELT: {
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H A D | SystemZISelLowering.cpp | 306 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); 386 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 387 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 4232 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I], 4346 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, 4376 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT, 4573 case ISD::INSERT_VECTOR_ELT:
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 495 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 666 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 2365 case ISD::INSERT_VECTOR_ELT: 5700 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, 6387 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); 6405 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we 6436 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); 6447 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); 6472 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec, 8700 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT) [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 660 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 767 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 813 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 929 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 1108 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 1302 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom); 1303 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom); 1396 setOperationAction(ISD::INSERT_VECTOR_ELT, V [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 517 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 1136 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1148 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 2530 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2532 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 4479 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4483 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 7068 /// ISD::INSERT_VECTOR_ELT. 7088 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, 7940 case ISD::INSERT_VECTOR_ELT [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 433 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 2836 case ISD::INSERT_VECTOR_ELT:
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/external/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1719 case InsertElement: return ISD::INSERT_VECTOR_ELT;
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1006 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo, 1012 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
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