Searched refs:INSERT_VECTOR_ELT (Results 1 - 25 of 35) sorted by relevance

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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DISDOpcodes.h255 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
258 INSERT_VECTOR_ELT, enumerator in enum:llvm::ISD::NodeType
/external/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp339 if (ISD == ISD::INSERT_VECTOR_ELT)
347 ISD == ISD::INSERT_VECTOR_ELT)
/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h271 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
274 INSERT_VECTOR_ELT, enumerator in enum:llvm::ISD::NodeType
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp446 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx);
450 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx);
H A DLegalizeVectorTypes.cpp59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
602 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
989 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
993 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
2064 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2302 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2832 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
3481 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
H A DSelectionDAGDumper.cpp218 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
H A DLegalizeIntegerTypes.cpp96 case ISD::INSERT_VECTOR_ELT:
892 case ISD::INSERT_VECTOR_ELT:
2753 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
3388 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
H A DLegalizeDAG.cpp93 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
310 /// INSERT_VECTOR_ELT instruction. In this case, it
2988 case ISD::INSERT_VECTOR_ELT:
4001 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4316 case ISD::INSERT_VECTOR_ELT: {
4359 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
/external/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp171 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
172 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
173 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
174 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
199 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
618 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
910 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
1996 case ISD::INSERT_VECTOR_ELT: {
H A DSIISelLowering.cpp147 case ISD::INSERT_VECTOR_ELT:
171 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
172 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp364 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx);
367 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx);
H A DLegalizeVectorTypes.cpp58 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
429 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
654 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
657 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
1238 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1418 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1872 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
2254 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
H A DLegalizeIntegerTypes.cpp83 case ISD::INSERT_VECTOR_ELT:
766 case ISD::INSERT_VECTOR_ELT:
2431 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2978 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86ISelLowering.cpp121 /// lowering INSERT_VECTOR_ELT operations easier.
701 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
871 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
875 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
941 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
942 setOperationAction(ISD::INSERT_VECTOR_ELT, MV
[all...]
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp101 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
626 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
1490 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1504 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
3287 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3290 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
5763 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5782 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
5833 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5846 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, d
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1954 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
1980 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
2493 // When there are non constant operands, add them with INSERT_VECTOR_ELT to
2678 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2772 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp257 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
306 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
1941 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
2344 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2403 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2413 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1311 case ISD::INSERT_VECTOR_ELT: {
H A DSystemZISelLowering.cpp306 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
386 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
387 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
4232 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I],
4346 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL,
4376 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT,
4573 case ISD::INSERT_VECTOR_ELT:
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp495 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
666 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
2365 case ISD::INSERT_VECTOR_ELT:
5700 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6387 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
6405 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
6436 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6447 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6472 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
8700 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
[all...]
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp660 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
767 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
813 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
929 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1108 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1302 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1303 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1396 setOperationAction(ISD::INSERT_VECTOR_ELT, V
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMISelLowering.cpp517 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
1136 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1148 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2530 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2532 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
4479 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4483 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
7068 /// ISD::INSERT_VECTOR_ELT.
7088 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
7940 case ISD::INSERT_VECTOR_ELT
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
H A DSPUISelLowering.cpp433 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
2836 case ISD::INSERT_VECTOR_ELT:
/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1719 case InsertElement: return ISD::INSERT_VECTOR_ELT;
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1006 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo,
1012 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,

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