| /external/vixl/test/aarch32/ |
| H A D | test-simulator-cond-rd-rn-rm-ge-a32.cc | 477 __ Msr(APSR_nzcvq, nzcv_bits);
489 __ Msr(APSR_nzcvq, q_bit);
495 __ Msr(APSR_g, ge_bits);
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| H A D | test-simulator-cond-rd-rn-rm-ge-t32.cc | 477 __ Msr(APSR_nzcvq, nzcv_bits);
489 __ Msr(APSR_nzcvq, q_bit);
495 __ Msr(APSR_g, ge_bits);
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| H A D | test-simulator-cond-rd-rn-rm-q-a32.cc | 461 __ Msr(APSR_nzcvq, nzcv_bits);
473 __ Msr(APSR_nzcvq, q_bit);
479 __ Msr(APSR_g, ge_bits);
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| H A D | test-simulator-cond-rd-rn-rm-q-t32.cc | 461 __ Msr(APSR_nzcvq, nzcv_bits);
473 __ Msr(APSR_nzcvq, q_bit);
479 __ Msr(APSR_g, ge_bits);
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| H A D | test-simulator-cond-rd-rn-rm-sel-a32.cc | 454 __ Msr(APSR_nzcvq, nzcv_bits);
466 __ Msr(APSR_nzcvq, q_bit);
472 __ Msr(APSR_g, ge_bits);
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| H A D | test-simulator-cond-rd-rn-rm-sel-t32.cc | 454 __ Msr(APSR_nzcvq, nzcv_bits);
466 __ Msr(APSR_nzcvq, q_bit);
472 __ Msr(APSR_g, ge_bits);
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| H A D | test-simulator-cond-rd-operand-const-a32.cc | 523 __ Msr(APSR_nzcvq, nzcv_bits);
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| H A D | test-simulator-cond-rd-operand-const-t32.cc | 638 __ Msr(APSR_nzcvq, nzcv_bits);
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| H A D | test-simulator-cond-rd-operand-imm16-t32.cc | 476 __ Msr(APSR_nzcvq, nzcv_bits);
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| H A D | test-simulator-cond-rd-operand-rn-a32.cc | 560 __ Msr(APSR_nzcvq, nzcv_bits);
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| H A D | test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 625 __ Msr(APSR_nzcvq, nzcv_bits);
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| H A D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 625 __ Msr(APSR_nzcvq, nzcv_bits);
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| H A D | test-simulator-cond-rd-operand-rn-t32.cc | 560 __ Msr(APSR_nzcvq, nzcv_bits);
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| H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 919 __ Msr(APSR_nzcvq, nzcv_bits);
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| H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 919 __ Msr(APSR_nzcvq, nzcv_bits);
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| H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 929 __ Msr(APSR_nzcvq, nzcv_bits);
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| H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 929 __ Msr(APSR_nzcvq, nzcv_bits);
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| H A D | test-simulator-cond-rdlow-operand-imm8-t32.cc | 1628 __ Msr(APSR_nzcvq, nzcv_bits);
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| H A D | test-disasm-a32.cc | 2401 // Msr with immediate for T32.
2402 COMPARE_T32(Msr(APSR_nzcvq, 0x0),
2407 COMPARE_BOTH(Msr(APSR_nzcvq, 0xbadbeef),
2413 MUST_FAIL_TEST_BOTH(Msr(APSR_nzcvq, Operand(r0, LSR, r1)),
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| H A D | test-simulator-cond-rd-rn-rm-a32.cc | 1565 __ Msr(APSR_nzcvq, nzcv_bits);
1577 __ Msr(APSR_nzcvq, q_bit);
1583 __ Msr(APSR_g, ge_bits);
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| H A D | test-simulator-cond-rd-rn-rm-t32.cc | 1563 __ Msr(APSR_nzcvq, nzcv_bits);
1575 __ Msr(APSR_nzcvq, q_bit);
1581 __ Msr(APSR_g, ge_bits);
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| H A D | test-assembler-aarch32.cc | 140 __ Msr(APSR_nzcvq, r0); \
2790 __ Msr(APSR_nzcvqg, 0);
2792 __ Msr(APSR_nzcvqg, 0xffffffff);
2796 __ Msr(APSR_nzcvq, r4);
2965 __ Msr(APSR_nzcvqg, r0);
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| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 1159 __ Msr(APSR_nzcvq, nzcv_bits);
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| /external/v8/src/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 982 void MacroAssembler::Msr(SystemRegister sysreg, const Register& rt) { function in class:v8::internal::MacroAssembler
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| H A D | macro-assembler-arm64.h | 498 inline void Msr(SystemRegister sysreg, const Register& rt);
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