/external/pcre/dist2/src/sljit/ |
H A D | sljitNativeMIPS_64.c | 38 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar); 45 return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SLJIT_SUCCESS; 81 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 32), dst_ar)); 89 return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar); 114 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 48), dst_ar)); 118 return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar); 234 FAIL_IF(push_inst(compiler, ORI | SA(0) | T(dst) | IMM((op & SLJIT_I32_OP) ? 32 : 64), UNMOVABLE_INS)); 257 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(ULESS_FLAG) | IMM(src2), ULESS_FLAG)); 293 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(OVERFLOW_FLAG) | IMM(src2), OVERFLOW_FLAG)); 415 EMIT_LOGICAL(ORI, O [all...] |
H A D | sljitNativePPC_64.c | 55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); 59 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; 77 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp >> 32))); 89 return push_inst(compiler, ORI | S(reg) | A(reg) | tmp2); 96 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp2)) : SLJIT_SUCCESS; 107 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | (tmp2 >> 48))); 113 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm >> 32))); 116 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)); 312 return push_inst(compiler, ORI | S(src1) | A(dst) | compiler->imm); 320 FAIL_IF(push_inst(compiler, ORI | [all...] |
H A D | sljitNativePPC_32.c | 35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); 38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; 185 return push_inst(compiler, ORI | S(src1) | A(dst) | compiler->imm); 193 FAIL_IF(push_inst(compiler, ORI | S(src1) | A(dst) | IMM(compiler->imm))); 250 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(init_value));
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H A D | sljitNativeMIPS_32.c | 32 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar); 38 return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SLJIT_SUCCESS; 142 FAIL_IF(push_inst(compiler, ORI | SA(0) | T(dst) | IMM(32), UNMOVABLE_INS)); 165 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(ULESS_FLAG) | IMM(src2), ULESS_FLAG)); 201 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(OVERFLOW_FLAG) | IMM(src2), OVERFLOW_FLAG)); 320 EMIT_LOGICAL(ORI, OR); 347 return push_inst(compiler, ORI | S(dst) | T(dst) | IMM(init_value), DR(dst));
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H A D | sljitNativeTILEGX_64.c | 424 #define ORI(dst, srca, imm) \ macro 1673 FAIL_IF(ORI(ULESS_FLAG ,reg_map[src1], src2)); 1735 FAIL_IF(ORI(TMP_EREG1, reg_map[src1], src2));
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/external/valgrind/none/tests/mips64/ |
H A D | logical_instructions.c | 7 OR, ORI, XOR, XORI enumerator in enum:__anon29709 68 case ORI:
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
H A D | MBlazeAsmBackend.cpp | 74 case MBlaze::ORI: return MBlaze::ORI32;
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 97 // transform this into the appropriate ORI instruction. 136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 379 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 590 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 668 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
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H A D | PPCRegisterInfo.cpp | 293 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 605 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
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H A D | PPCISelLowering.cpp | 4811 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 5145 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 301 // transform this into the appropriate ORI instruction. 351 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 355 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 377 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 765 : PPC::ORI ); 1141 : PPC::ORI ); 1829 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
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H A D | PPCFastISel.cpp | 1225 Opc = PPC::ORI; 2025 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
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H A D | PPCRegisterInfo.cpp | 893 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
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H A D | PPCISelDAGToDAG.cpp | 4030 // For ORI and ORIS, we need the higher-order bits of the first operand to be 4033 if (Op32.getMachineOpcode() == PPC::ORI || 4191 case PPC::ORI: NewOpcode = PPC::ORI8; break;
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/external/v8/src/mips/ |
H A D | constants-mips.h | 357 ORI = ((1U << 3) + 5) << kOpcodeShift, 909 OpcodeToBitNumber(ANDI) | OpcodeToBitNumber(ORI) |
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H A D | assembler-mips.cc | 621 return opcode == ORI; 1692 GenInstrImmediate(ORI, rs, rt, j); 3275 *(p + 1) = ORI | rt_code | (rt_code << 5) | (itarget & kImm16Mask);
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/external/v8/src/mips64/ |
H A D | assembler-mips64.cc | 593 return opcode == ORI; 1776 GenInstrImmediate(ORI, rs, rt, j); 3462 if ((GetOpcodeField(instr0) == LUI) && (GetOpcodeField(instr1) == ORI) && 3463 (GetOpcodeField(instr3) == ORI)) { 3518 CHECK((GetOpcodeField(instr0) == LUI && GetOpcodeField(instr1) == ORI && 3519 GetOpcodeField(instr3) == ORI)); 3528 *(p + 1) = ORI | (rt_code << kRtShift) | (rt_code << kRsShift) 3530 *(p + 3) = ORI | (rt_code << kRsShift) | (rt_code << kRtShift)
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H A D | constants-mips64.h | 328 ORI = ((1U << 3) + 5) << kOpcodeShift, 942 OpcodeToBitNumber(ORI) | OpcodeToBitNumber(XORI) |
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/external/v8/src/ppc/ |
H A D | assembler-ppc.cc | 311 bool Assembler::IsOri(Instr instr) { return (instr & kOpcodeMask) == ORI; } 470 instr = ORI; // nop: ori, 0,0,0 483 instr = ORI; // nop: ori, 0,0,0 1003 d_form(ORI, rs, ra, imm.imm_, false); 2413 return instr == (ORI | reg * B21 | reg * B16);
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H A D | simulator-ppc.cc | 45 static const Instr kNopInstr = (ORI); // ori, 0,0,0 3630 case ORI: {
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H A D | constants-ppc.h | 1727 V(ori, ORI, 0x60000000) \
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/external/icu/icu4c/source/common/ |
H A D | ucnvisci.cpp | 94 ORI = 0x47, enumerator in enum:__anon7945 147 { ORIYA, ORI_MASK, ORI }, 279 * | DEV | PNJ | GJR | ORI | BNG | TLG | MLM | TML |
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
H A D | MBlazeDisassembler.cpp | 53 MBlaze::ORI, MBlaze::ANDI, MBlaze::XORI, MBlaze::ANDNI, //28,29,2A,2B
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/external/icu/icu4j/main/classes/charset/src/com/ibm/icu/charset/ |
H A D | CharsetISCII.java | 86 static final short ORI = 0x47; field in class:CharsetISCII.ISCIILang 165 new LookupDataStruct(UniLang.ORIYA, MaskEnum.ORI_MASK, ISCIILang.ORI), 176 * |DEV | PNJ | GJR | ORI | BNG | TLG | MLM | TML |
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/external/capstone/arch/PowerPC/ |
H A D | PPCGenAsmWriter.inc | 771 19678U, // ORI 2044 1U, // ORI 3956 // ANDISo, ANDISo8, ANDIo, ANDIo8, CMPLDI, CMPLWI, ORI, ORI8, ORIS, ORIS8...
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