Searched refs:ORI (Results 1 - 25 of 32) sorted by relevance

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/external/pcre/dist2/src/sljit/
H A DsljitNativeMIPS_64.c38 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar);
45 return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SLJIT_SUCCESS;
81 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 32), dst_ar));
89 return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar);
114 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 48), dst_ar));
118 return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar);
234 FAIL_IF(push_inst(compiler, ORI | SA(0) | T(dst) | IMM((op & SLJIT_I32_OP) ? 32 : 64), UNMOVABLE_INS));
257 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(ULESS_FLAG) | IMM(src2), ULESS_FLAG));
293 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(OVERFLOW_FLAG) | IMM(src2), OVERFLOW_FLAG));
415 EMIT_LOGICAL(ORI, O
[all...]
H A DsljitNativePPC_64.c55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm));
59 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS;
77 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp >> 32)));
89 return push_inst(compiler, ORI | S(reg) | A(reg) | tmp2);
96 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp2)) : SLJIT_SUCCESS;
107 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | (tmp2 >> 48)));
113 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm >> 32)));
116 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm));
312 return push_inst(compiler, ORI | S(src1) | A(dst) | compiler->imm);
320 FAIL_IF(push_inst(compiler, ORI |
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H A DsljitNativePPC_32.c35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm));
38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS;
185 return push_inst(compiler, ORI | S(src1) | A(dst) | compiler->imm);
193 FAIL_IF(push_inst(compiler, ORI | S(src1) | A(dst) | IMM(compiler->imm)));
250 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(init_value));
H A DsljitNativeMIPS_32.c32 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar);
38 return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SLJIT_SUCCESS;
142 FAIL_IF(push_inst(compiler, ORI | SA(0) | T(dst) | IMM(32), UNMOVABLE_INS));
165 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(ULESS_FLAG) | IMM(src2), ULESS_FLAG));
201 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(OVERFLOW_FLAG) | IMM(src2), OVERFLOW_FLAG));
320 EMIT_LOGICAL(ORI, OR);
347 return push_inst(compiler, ORI | S(dst) | T(dst) | IMM(init_value), DR(dst));
H A DsljitNativeTILEGX_64.c424 #define ORI(dst, srca, imm) \ macro
1673 FAIL_IF(ORI(ULESS_FLAG ,reg_map[src1], src2));
1735 FAIL_IF(ORI(TMP_EREG1, reg_map[src1], src2));
/external/valgrind/none/tests/mips64/
H A Dlogical_instructions.c7 OR, ORI, XOR, XORI enumerator in enum:__anon29709
68 case ORI:
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
H A DMBlazeAsmBackend.cpp74 case MBlaze::ORI: return MBlaze::ORI32;
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp97 // transform this into the appropriate ORI instruction.
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
379 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
590 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
668 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
H A DPPCRegisterInfo.cpp293 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
605 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
H A DPPCISelLowering.cpp4811 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
5145 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
/external/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp301 // transform this into the appropriate ORI instruction.
351 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
355 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
377 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
765 : PPC::ORI );
1141 : PPC::ORI );
1829 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
H A DPPCFastISel.cpp1225 Opc = PPC::ORI;
2025 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
H A DPPCRegisterInfo.cpp893 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
H A DPPCISelDAGToDAG.cpp4030 // For ORI and ORIS, we need the higher-order bits of the first operand to be
4033 if (Op32.getMachineOpcode() == PPC::ORI ||
4191 case PPC::ORI: NewOpcode = PPC::ORI8; break;
/external/v8/src/mips/
H A Dconstants-mips.h357 ORI = ((1U << 3) + 5) << kOpcodeShift,
909 OpcodeToBitNumber(ANDI) | OpcodeToBitNumber(ORI) |
H A Dassembler-mips.cc621 return opcode == ORI;
1692 GenInstrImmediate(ORI, rs, rt, j);
3275 *(p + 1) = ORI | rt_code | (rt_code << 5) | (itarget & kImm16Mask);
/external/v8/src/mips64/
H A Dassembler-mips64.cc593 return opcode == ORI;
1776 GenInstrImmediate(ORI, rs, rt, j);
3462 if ((GetOpcodeField(instr0) == LUI) && (GetOpcodeField(instr1) == ORI) &&
3463 (GetOpcodeField(instr3) == ORI)) {
3518 CHECK((GetOpcodeField(instr0) == LUI && GetOpcodeField(instr1) == ORI &&
3519 GetOpcodeField(instr3) == ORI));
3528 *(p + 1) = ORI | (rt_code << kRtShift) | (rt_code << kRsShift)
3530 *(p + 3) = ORI | (rt_code << kRsShift) | (rt_code << kRtShift)
H A Dconstants-mips64.h328 ORI = ((1U << 3) + 5) << kOpcodeShift,
942 OpcodeToBitNumber(ORI) | OpcodeToBitNumber(XORI) |
/external/v8/src/ppc/
H A Dassembler-ppc.cc311 bool Assembler::IsOri(Instr instr) { return (instr & kOpcodeMask) == ORI; }
470 instr = ORI; // nop: ori, 0,0,0
483 instr = ORI; // nop: ori, 0,0,0
1003 d_form(ORI, rs, ra, imm.imm_, false);
2413 return instr == (ORI | reg * B21 | reg * B16);
H A Dsimulator-ppc.cc45 static const Instr kNopInstr = (ORI); // ori, 0,0,0
3630 case ORI: {
H A Dconstants-ppc.h1727 V(ori, ORI, 0x60000000) \
/external/icu/icu4c/source/common/
H A Ducnvisci.cpp94 ORI = 0x47, enumerator in enum:__anon7945
147 { ORIYA, ORI_MASK, ORI },
279 * | DEV | PNJ | GJR | ORI | BNG | TLG | MLM | TML |
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/
H A DMBlazeDisassembler.cpp53 MBlaze::ORI, MBlaze::ANDI, MBlaze::XORI, MBlaze::ANDNI, //28,29,2A,2B
/external/icu/icu4j/main/classes/charset/src/com/ibm/icu/charset/
H A DCharsetISCII.java86 static final short ORI = 0x47; field in class:CharsetISCII.ISCIILang
165 new LookupDataStruct(UniLang.ORIYA, MaskEnum.ORI_MASK, ISCIILang.ORI),
176 * |DEV | PNJ | GJR | ORI | BNG | TLG | MLM | TML |
/external/capstone/arch/PowerPC/
H A DPPCGenAsmWriter.inc771 19678U, // ORI
2044 1U, // ORI
3956 // ANDISo, ANDISo8, ANDIo, ANDIo8, CMPLDI, CMPLWI, ORI, ORI8, ORIS, ORIS8...

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