/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | Analysis.cpp | 155 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 163 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 186 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 525 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 526 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 539 CCs[RTLIB::O_F32] = ISD::SETEQ; 540 CCs[RTLIB::O_F64] = ISD::SETEQ; 1938 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1940 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1947 Cond = ISD::SETEQ; 1972 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1981 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2084 case ISD::SETEQ [all...] |
H A D | LegalizeIntegerTypes.cpp | 815 case ISD::SETEQ: 2009 ISD::SETEQ : ISD::SETNE); 2476 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 2558 LHSHi, RHSHi, ISD::SETEQ, false, 2562 LHSHi, RHSHi, ISD::SETEQ);
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H A D | SelectionDAGBuilder.cpp | 1340 Condition = ISD::SETEQ; // silence warning. 1352 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1436 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1526 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1547 CB.CC == ISD::SETEQ) 1550 CB.CC == ISD::SETEQ) { 1753 ISD::SETEQ); 1924 ISD::SETEQ); 1978 CC = ISD::SETEQ;
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H A D | LegalizeFloatTypes.cpp | 623 case ISD::SETEQ: 906 DAG.getCondCode(ISD::SETEQ));
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 707 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 732 SETEQ, // 1 X 0 0 1 True if equal enumerator in enum:llvm::ISD::CondCode
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 161 case ISD::SETEQ: 1293 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) 1382 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1384 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1391 Cond = ISD::SETEQ; 1416 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1425 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1492 bool Inverse = (N1C->isNullValue() && Cond == ISD::SETEQ) || 1579 case ISD::SETEQ: return DAG.getConstant(0, dl, VT); 1598 case ISD::SETEQ [all...] |
H A D | LegalizeIntegerTypes.cpp | 949 case ISD::SETEQ: 1367 N->getOperand(2), ISD::SETEQ); 1620 ISD::SETEQ); 1713 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ); 2285 ISD::SETEQ : ISD::SETNE); 2557 RHS, DAG.getConstant(0, dl, VT), ISD::SETEQ); 2799 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 2927 LHSHi, RHSHi, ISD::SETEQ, false, 2931 LHSHi, RHSHi, ISD::SETEQ);
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H A D | SelectionDAGDumper.cpp | 347 case ISD::SETEQ: return "seteq";
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H A D | LegalizeDAG.cpp | 1630 case ISD::SETEQ: 1632 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ; 2694 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ); 2860 DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ); 3348 ISD::SETEQ : ISD::SETNE);
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 453 if (CC == ISD::SETEQ || CC == ISD::SETNE) { 455 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 494 if (CC == ISD::SETEQ || CC == ISD::SETNE) { 496 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 553 case ISD::SETEQ: return PPC::PRED_EQ; 588 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ 624 case ISD::SETEQ: { 653 case ISD::SETEQ:
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H A D | PPCISelLowering.cpp | 1238 if (C->isNullValue() && CC == ISD::SETEQ) { 1264 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 3579 // Cannot handle SETEQ/SETNE. 3580 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 5401 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 5409 if (CC == ISD::SETEQ) // Cond never true, remove branch. 5416 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 845 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 870 SETEQ, // 1 X 0 0 1 True if equal enumerator in enum:llvm::ISD::CondCode
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/external/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 186 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; 201 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
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H A D | TargetLoweringBase.cpp | 763 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 764 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 765 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 766 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; 791 CCs[RTLIB::O_F32] = ISD::SETEQ; 792 CCs[RTLIB::O_F64] = ISD::SETEQ; 793 CCs[RTLIB::O_F128] = ISD::SETEQ; 794 CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
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/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 970 case ISD::SETEQ: 1374 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ); 1378 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ); 1448 ISD::SETEQ); 1462 ISD::SETEQ); 1499 Quotient, Quotient_A_One, ISD::SETEQ); 1503 Quotient_S_One, Div, ISD::SETEQ); 1515 Remainder, Remainder_S_Den, ISD::SETEQ); 1519 Remainder_A_Den, Rem, ISD::SETEQ); 1797 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ); [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 1992 if (CC == ISD::SETEQ || CC == ISD::SETNE) { 1994 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 2036 if (CC == ISD::SETEQ || CC == ISD::SETNE) { 2038 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 2098 case ISD::SETEQ: return PPC::PRED_EQ; 2129 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ 2170 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; 2178 case ISD::SETEQ: 2214 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; 2222 case ISD::SETEQ [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
H A D | AlphaISelDAGToDAG.cpp | 311 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
H A D | PTXISelLowering.cpp | 161 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
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/external/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 794 // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT, 799 case ISD::SETEQ: 1270 SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 648 case ISD::SETEQ: return SPCC::ICC_E; 666 case ISD::SETEQ:
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/external/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 560 case ISD::SETEQ:
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/external/llvm/lib/Target/X86/ |
H A D | X86IntrinsicsInfo.h | 1862 X86_INTRINSIC_DATA(sse_comieq_ss, COMI, X86ISD::COMI, ISD::SETEQ), 1874 X86_INTRINSIC_DATA(sse_ucomieq_ss, COMI, X86ISD::UCOMI, ISD::SETEQ), 1880 X86_INTRINSIC_DATA(sse2_comieq_sd, COMI, X86ISD::COMI, ISD::SETEQ), 1924 X86_INTRINSIC_DATA(sse2_ucomieq_sd, COMI, X86ISD::UCOMI, ISD::SETEQ),
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 619 case ISD::SETEQ:
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 199 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ }, 209 { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ }, 274 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ }, 280 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ }, 292 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ }, 298 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ }, 1333 case ISD::SETEQ: return ARMCC::EQ; 1351 case ISD::SETEQ: 4027 CC = ISD::SETEQ; 4091 (CC == ISD::SETEQ || C [all...] |