/drivers/usb/host/ |
H A D | fotg210.h | 300 u32 control; member in struct:fotg210_dbg_port 364 * used with control, bulk, and interrupt transfers. 450 * QH: describes control/bulk/interrupt endpoints 460 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ 462 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
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H A D | fusbh200.h | 292 u32 control; member in struct:fusbh200_dbg_port 356 * used with control, bulk, and interrupt transfers. 440 * QH: describes control/bulk/interrupt endpoints 450 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ 452 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
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H A D | ohci.h | 84 * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt) 210 /* control and status registers (section 7.1) */ 212 __hc32 control; member in struct:ohci_regs 251 * HcControl (control) register masks 253 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ 256 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */ 273 #define OHCI_CLF (1 << 1) /* control list filled */ 321 #define RH_B_PPCM 0xffff0000 /* port power control mask */ 401 u32 hc_control; /* copy of hc control reg */
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H A D | oxu210hp.h | 75 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 171 u32 control; member in struct:ehci_dbg_port 201 * used with control, bulk, and interrupt transfers. 270 * QH: describes control/bulk/interrupt endpoints
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H A D | u132-hcd.c | 441 retval = u132_read_pcimem(u132, control, &u132->hc_control); 1570 u32 control; local 1576 retval = u132_read_pcimem(u132, control, &control); 1603 u32 control; local 1622 retval = u132_read_pcimem(u132, control, &u132->hc_control); 1625 dev_info(&u132->platform_dev->dev, "resetting from state '%s', control " 1644 retval = u132_write_pcimem(u132, control, u132->hc_control); 1647 retval = u132_read_pcimem(u132, control, &control); 3091 u32 control; local [all...] |
/drivers/usb/misc/ |
H A D | ftdi-elan.c | 2269 u32 control; local 2284 retval = ftdi_read_pcimem(ftdi, control, &control); 2298 retval = ftdi_read_pcimem(ftdi, control, &hc_control); 2317 retval = ftdi_write_pcimem(ftdi, control, hc_control); 2320 retval = ftdi_read_pcimem(ftdi, control, &control); 2335 retval = ftdi_read_pcimem(ftdi, control, &control); 2359 retval = ftdi_write_pcimem(ftdi, control, hc_contro [all...] |
/drivers/video/fbdev/ |
H A D | cg6.c | 66 * The FBC could be the frame buffer control 67 * The FHC could is the frame buffer hardware control. 250 u32 control; member in struct:bt_regs 657 sbus_writel(0xff << 24, &bt->control); 659 sbus_writel(0x00 << 24, &bt->control); 661 sbus_writel(0x73 << 24, &bt->control); 663 sbus_writel(0x00 << 24, &bt->control);
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/drivers/block/ |
H A D | nvme-core.c | 664 u16 control; local 676 control = 0; 678 control |= NVME_RW_FUA; 680 control |= NVME_RW_LR; 697 cmnd->rw.control = cpu_to_le16(control); 1602 c.rw.control = cpu_to_le16(io.control);
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/drivers/char/ |
H A D | mbcs.h | 346 union cm_control control; member in struct:cm_mmr 412 union dma_control control; member in struct:rdma_mmr 433 union dma_control control; member in struct:wdma_mmr
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/drivers/firewire/ |
H A D | ohci.c | 79 __le16 control; member in struct:descriptor 1032 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1065 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1173 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1265 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) == 1320 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1363 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1411 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 2792 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2804 if (last->control 2865 __le16 control; local 3051 u32 control = IR_CONTEXT_ISOCH_HEADER, match; local [all...] |
/drivers/gpu/drm/i915/ |
H A D | intel_dp.c | 1281 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1287 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1339 u32 control; local 1343 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1344 control &= ~PANEL_UNLOCK_MASK; 1345 control |= PANEL_UNLOCK_REGS; 1346 return control; 1622 /* Enable backlight in the panel power control. */ 1652 /* Enable backlight PWM and backlight PP control. */ 1664 /* Disable backlight in the panel power control [all...] |
H A D | intel_drv.h | 354 u32 control; member in struct:intel_crtc_config::__anon716
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/drivers/iommu/ |
H A D | amd_iommu.c | 2196 u16 control; local 2203 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); 2204 control |= PCI_PRI_CTRL_RESET; 2205 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
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/drivers/media/platform/ |
H A D | vino.c | 1842 ctrl = vino->control; 1925 vino->control = ctrl; 1933 u32 ctrl = vino->control; 1938 vino->control = ctrl; 1944 u32 ctrl = vino->control; 1950 vino->control = ctrl; 2468 ctrl = vino->control; 2469 vino->control = ctrl & ~(VINO_CTRL_A_INT | VINO_CTRL_B_INT); 2471 vino->control = ctrl; 3659 struct v4l2_control *control) 3658 vino_g_ctrl(struct file *file, void *__fh, struct v4l2_control *control) argument 3714 vino_s_ctrl(struct file *file, void *__fh, struct v4l2_control *control) argument [all...] |
/drivers/net/ethernet/nxp/ |
H A D | lpc_eth.c | 380 /* Receive Descriptor control word */ 394 /* Transmit Descriptor control word */ 408 __le32 control; member in struct:txrx_desc_t 600 ptxrxdesc->control = 0; 611 ptxrxdesc->control = RXDESC_CONTROL_INT | (ENET_MAXF_SIZE - 1); 1103 /* Setup control for the transfer */ 1107 ptxrxdesc->control =
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/drivers/net/ethernet/ti/ |
H A D | cpsw.c | 175 u32 control; member in struct:cpsw_wr_regs 194 u32 control; member in struct:cpsw_ss_regs 1188 control_reg = readl(&priv->regs->control); 1190 writel(control_reg, &priv->regs->control); 1269 /* Enable internal fifo flow control */
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/drivers/net/wireless/b43/ |
H A D | main.c | 90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 485 u32 control; local 488 control = routing; 489 control <<= 16; 490 control |= offset; 491 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 1573 /* Convert a b43 antenna number value to the PHY TX control value. */ 1614 /* Write the PHY TX control parameters. */ 3225 /* Initialize the MAC control */ 3606 struct ieee80211_tx_control *control, 3605 b43_op_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb) argument [all...] |
/drivers/net/wireless/ipw2x00/ |
H A D | libipw.h | 58 /* QOS control */ 234 u8 control; member in struct:libipw_rx_stats
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/drivers/net/wireless/libertas/ |
H A D | host.h | 305 /* Tx control */ 316 /* Pkt Trasnit Power control */ 341 /* Tx control */ 578 __le16 control; member in struct:cmd_ds_802_11_radio_control 604 /* control periodic calibration */ 607 /* control the use of external sleep clock */ 815 /* key control Info specific to a keytypeid */
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/drivers/net/wireless/rt2x00/ |
H A D | rt2x00.h | 554 * Radio control handlers. 579 * TX control handlers 591 * RX control handlers 749 * IEEE80211 control structure. 1014 __le16 control; member in struct:rt2x00_bar_list_entry 1414 struct ieee80211_tx_control *control,
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/drivers/net/wireless/ti/wlcore/ |
H A D | main.c | 1240 struct ieee80211_tx_control *control, 1245 struct ieee80211_vif *vif = info->control.vif; 1261 hlid = wl12xx_tx_get_hlid(wl, wlvif, skb, control->sta); 5145 mask->control[NL80211_BAND_2GHZ].legacy, 5146 mask->control[NL80211_BAND_5GHZ].legacy); 5153 mask->control[i].legacy, 1239 wl1271_op_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb) argument
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/drivers/pci/ |
H A D | pci.c | 2292 * Except for egress control, capabilities are either required 3085 u16 control; local 3094 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 3095 control &= ~PCI_MSI_FLAGS_ENABLE; 3096 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 3100 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 3101 control &= ~PCI_MSIX_FLAGS_ENABLE; 3102 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 3270 * Use the bridge control register to assert reset on the secondary bus. 3774 * control [all...] |
/drivers/scsi/aic7xxx/ |
H A D | aic7xxx_core.c | 553 hscb->control = 0; 1108 sc->control = 0; 1117 hscb->control = 0; 1134 hscb->control |= MK_MESSAGE; 1923 if ((scb->hscb->control & TAG_ENB) != 0) 2107 printk("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2109 hscb->control, 2716 pending_hscb->control &= ~ULTRAENB; 2718 pending_hscb->control |= ULTRAENB; 2724 pending_hscb->control 2745 u_int control; local [all...] |
/drivers/scsi/ |
H A D | hpsa_cmd.h | 430 u32 control; /* 0x3C - 0x3F */ member in struct:io_accel1_cmd
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/drivers/scsi/lpfc/ |
H A D | lpfc_init.c | 1759 volatile uint32_t control; local 1815 control = readl(phba->HCregaddr); 1816 control |= HC_LAINT_ENA; 1817 writel(control, phba->HCregaddr); 4890 * the FCP rsp, and a BDE for each. Sice we have no control 5083 * the FCP rsp, and a SGE for each. Sice we have no control 6259 "ioremap failed for HBA control registers.\n"); 6553 * This routine is invoked to set up SLI4 BAR1 control status register (CSR) 8133 "ioremap failed for SLI4 HBA control registers.\n");
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