Searched refs:ctl (Results 76 - 100 of 227) sorted by relevance

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/drivers/tty/serial/
H A Dtimbuart.c84 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | local
87 iowrite8(ctl, port->membase + TIMBUART_CTRL);
170 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | local
172 iowrite8(ctl, port->membase + TIMBUART_CTRL);
247 static void timbuart_break_ctl(struct uart_port *port, int ctl) argument
/drivers/vme/bridges/
H A Dvme_ca91cx42.c436 /* Write ctl reg without enable */
451 unsigned int i, granularity = 0, ctl = 0; local
465 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
478 if (ctl & CA91CX42_VSI_CTL_EN)
481 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
483 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
485 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
487 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
489 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
492 if (ctl
760 unsigned int i, ctl; local
[all...]
/drivers/edac/
H A Dmv64x60_edac.c667 u32 ctl; local
671 ctl = in_le32(pdata->mc_vbase + MV64X60_SDRAM_CONFIG);
679 dimm->mtype = (ctl & MV64X60_SDRAM_REGISTERED) ? MEM_RDDR : MEM_DDR;
681 devtype = (ctl >> 20) & 0x3;
706 u32 ctl; local
761 ctl = in_le32(pdata->mc_vbase + MV64X60_SDRAM_CONFIG);
762 if (!(ctl & MV64X60_SDRAM_ECC)) {
788 ctl = in_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CNTL);
789 ctl = (ctl
[all...]
/drivers/media/usb/tm6000/
H A Dtm6000-cards.c932 struct xc2028_ctrl ctl; local
935 memset(&ctl, 0, sizeof(ctl));
937 ctl.demod = XC3028_FE_ZARLINK456;
940 xc2028_cfg.priv = &ctl;
946 ctl.max_len = 80;
947 ctl.fname = "xc3028L-v36.fw";
951 ctl.fname = "xc3028-v27.fw";
953 ctl.fname = "xc3028-v24.fw";
965 struct xc5000_config ctl local
[all...]
/drivers/ide/
H A Dscc_pata.c66 unsigned long ctl, dma; member in struct:scc_ports
151 static void scc_write_devctl(ide_hwif_t *hwif, u8 ctl) argument
153 out_be32((void *)hwif->io_ports.ctl_addr, ctl);
212 unsigned long ctl_base = ports->ctl;
244 unsigned long ctl_base = ports->ctl;
524 if (scc_ports[i].ctl == 0)
545 scc_ports[i].ctl = (unsigned long)ctl_addr;
609 ctl_base = ports->ctl;
729 hwif->config_data = ports->ctl;
855 iounmap((void*)ports->ctl);
[all...]
/drivers/video/fbdev/
H A Dbfin-lq035q1-fb.c143 struct spi_control *ctl; local
148 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
150 if (!ctl)
153 ctl->mode = (info->disp_info->mode &
157 ret |= lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode);
159 kfree(ctl);
163 spi_set_drvdata(spi, ctl);
184 struct spi_control *ctl = spi_get_drvdata(spi); local
187 ret = lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl
[all...]
/drivers/net/ethernet/smsc/
H A Dsmc91x.c249 unsigned int ctl, cfg; local
317 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
325 ctl |= CTL_AUTO_RELEASE;
327 ctl &= ~CTL_AUTO_RELEASE;
328 SMC_SET_CTL(lp, ctl);
591 * Send the packet length (+6 for status words, length, and ctl.
599 /* Send final ctl word with the last byte if there is one */
653 * words, length and ctl)
655 * If odd size then last byte is included in ctl word.
1191 unsigned int ctl; local
1631 u16 ctl; local
1659 u16 ctl; local
[all...]
/drivers/net/wireless/b43/
H A Ddma.c105 u32 ctl; local
115 ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
117 ctl |= B43_DMA32_DCTL_DTABLEEND;
119 ctl |= B43_DMA32_DCTL_FRAMESTART;
121 ctl |= B43_DMA32_DCTL_FRAMEEND;
123 ctl |= B43_DMA32_DCTL_IRQ;
124 ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
127 desc->dma32.control = cpu_to_le32(ctl);
1802 u32 ctl; local
1805 ctl
[all...]
H A Dlo.c789 memcpy(&cal->ctl, &loctl, sizeof(loctl));
863 val = (u8)(cal->ctl.q);
864 val |= ((u8)(cal->ctl.i)) << 4;
911 b43_lo_write(dev, &cal->ctl);
929 b43_lo_write(dev, &cal->ctl);
978 cal->ctl.i, cal->ctl.q);
990 b43_lo_write(dev, &cal->ctl);
/drivers/media/pci/cx88/
H A Dcx88-cards.c3365 void cx88_setup_xc3028(struct cx88_core *core, struct xc2028_ctrl *ctl) argument
3367 memset(ctl, 0, sizeof(*ctl));
3369 ctl->fname = XC2028_DEFAULT_FIRMWARE;
3370 ctl->max_len = 64;
3380 ctl->demod = XC3028_FE_ZARLINK456;
3384 ctl->demod = XC3028_FE_OREN538;
3392 ctl->disable_power_mgmt = 1;
3403 ctl->demod = XC3028_FE_ZARLINK456;
3404 ctl
3520 struct tea5767_ctrl ctl; local
3587 struct xc2028_ctrl ctl; local
[all...]
/drivers/media/platform/blackfin/
H A Dppi.c154 bfin_write32(&reg->ctl, ppi->ppi_control);
187 bfin_write32(&reg->ctl, ppi->ppi_control);
275 bfin_write32(&reg->ctl, ppi->ppi_control);
/drivers/ata/
H A Dacard-ahci.c133 u32 ctl; local
147 ctl = readl(mmio + HOST_CTL);
148 ctl &= ~HOST_IRQ_EN;
149 writel(ctl, mmio + HOST_CTL);
H A Dlibahci_platform.c524 u32 ctl; local
536 ctl = readl(mmio + HOST_CTL);
537 ctl &= ~HOST_IRQ_EN;
538 writel(ctl, mmio + HOST_CTL);
H A Dpata_octeon_cf.c414 iowrite8(tf->ctl | ATA_HOB, ap->ioaddr.ctl_addr);
427 iowrite8(tf->ctl, ap->ioaddr.ctl_addr);
428 ap->last_ctl = tf->ctl;
453 __raw_writew(ap->ctl, base + 0xe);
455 __raw_writew(ap->ctl | ATA_SRST, base + 0xe);
457 __raw_writew(ap->ctl, base + 0xe);
482 if (tf->ctl != ap->last_ctl) {
483 iowrite8(tf->ctl, ap->ioaddr.ctl_addr);
484 ap->last_ctl = tf->ctl;
1010 ata_port_desc(ap, "cmd %p ctl
[all...]
H A Dsata_promise.h85 buf[15] = tf->ctl;
H A Dlibata-sff.c117 * when finding an IRQ source. Non ctl capable devices don't
143 * If we have an mmio device with no ctl and no altstatus
163 * If we have an mmio device with no ctl and no altstatus
193 /* There are no DMA controllers without ctl. BUG here to ensure
286 * @ctl: value to write
296 static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl) argument
299 ap->ops->sff_set_devctl(ap, ctl);
301 iowrite8(ctl, ap->ioaddr.ctl_addr);
391 ap->ctl &= ~ATA_NIEN;
392 ap->last_ctl = ap->ctl;
[all...]
/drivers/media/pci/saa7164/
H A Dsaa7164-api.c368 int saa7164_api_set_usercontrol(struct saa7164_port *port, u8 ctl) argument
374 if (ctl == PU_BRIGHTNESS_CONTROL)
377 if (ctl == PU_CONTRAST_CONTROL)
380 if (ctl == PU_HUE_CONTROL)
383 if (ctl == PU_SATURATION_CONTROL)
386 if (ctl == PU_SHARPNESS_CONTROL)
391 dprintk(DBGLVL_ENC, "%s() unitid=0x%x ctl=%d, val=%d\n",
392 __func__, port->encunit.vsourceid, ctl, val);
395 ctl, sizeof(u16), &val);
402 int saa7164_api_get_usercontrol(struct saa7164_port *port, u8 ctl) argument
[all...]
/drivers/mmc/host/
H A Dtmio_mmc.c105 (unsigned long)host->ctl, irq);
/drivers/net/ethernet/sfc/
H A Dtxc43128_phy.c365 int ctl = efx_mdio_read(efx, mmd, TXC_GLRGS_GLCMD); local
368 ctl &= ~pd;
370 ctl |= pd;
372 efx_mdio_write(efx, mmd, TXC_GLRGS_GLCMD, ctl);
/drivers/net/wireless/iwlegacy/
H A D3945.h434 #define TFD_CTL_COUNT_GET(ctl) ((ctl >> 24) & 7)
436 #define TFD_CTL_PAD_GET(ctl) (ctl >> 28)
/drivers/thunderbolt/
H A Dswitch.c244 res.err = tb_cfg_write(tb->ctl, ((u32 *) &header) + 2, route,
248 res = tb_cfg_reset(tb->ctl, route, TB_CFG_DEFAULT_TIMEOUT);
344 int upstream_port = tb_cfg_get_upstream_port(tb->ctl, route);
353 if (tb_cfg_read(tb->ctl, &sw->config, route, 0, 2, 0, 5))
/drivers/crypto/amcc/
H A Dcrypto4xx_reg_def.h234 u32 ctl:30; member in struct:sd_ctl
241 struct sd_ctl ctl; member in struct:ce_sd
/drivers/spi/
H A Dspi-adi-v3.c113 u32 ctl; local
115 ctl = ioread32(&drv_data->regs->control);
116 ctl |= SPI_CTL_EN;
117 iowrite32(ctl, &drv_data->regs->control);
122 u32 ctl; local
124 ctl = ioread32(&drv_data->regs->control);
125 ctl &= ~SPI_CTL_EN;
126 iowrite32(ctl, &drv_data->regs->control);
/drivers/media/pci/ddbridge/
H A Dddbridge-core.c693 struct stv6110x_devctl *ctl; local
695 ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c);
696 if (!ctl) {
703 feconf->tuner_init = ctl->tuner_init;
704 feconf->tuner_sleep = ctl->tuner_sleep;
705 feconf->tuner_set_mode = ctl->tuner_set_mode;
706 feconf->tuner_set_frequency = ctl->tuner_set_frequency;
707 feconf->tuner_get_frequency = ctl->tuner_get_frequency;
708 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
709 feconf->tuner_get_bandwidth = ctl
[all...]
/drivers/clk/qcom/
H A Dclk-rcg.c427 u32 ns, md, ctl; local
448 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
449 ctl = mn_to_reg(mn, f->m, f->n, ctl);
450 regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);

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