/drivers/tty/serial/cpm_uart/ |
H A D | cpm_uart.h | 116 u32 val = (u32)addr; local 119 if (likely(val >= mem && val < mem + pinfo->mem_size)) { 120 offset = val - mem; 132 u32 val = addr; local 135 if (likely(val >= dma && val < dma + pinfo->mem_size)) { 136 offset = val - dma;
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/drivers/watchdog/ |
H A D | bcm_kona_wdt.c | 67 uint32_t val; local 78 val = readl_relaxed(wdt->base + offset); 80 } while ((val & SECWDOG_WD_LOAD_FLAG) && count < SECWDOG_MAX_TRY); 89 if (val & SECWDOG_WD_LOAD_FLAG) 93 val &= SECWDOG_RESERVED_MASK; 95 return val; 188 int val; local 194 val = secure_register_read(wdt, SECWDOG_CTRL_REG); 195 if (val < 0) { 196 ret = val; 237 int val; local [all...] |
/drivers/pci/host/ |
H A D | pci-xgene.c | 78 static inline void xgene_pcie_cfg_out32(void __iomem *addr, int offset, u32 val) argument 80 writel(val, addr + offset); 83 static inline void xgene_pcie_cfg_out16(void __iomem *addr, int offset, u16 val) argument 90 val32 |= (u32)val << 16; 95 val32 |= val; 101 static inline void xgene_pcie_cfg_out8(void __iomem *addr, int offset, u8 val) argument 108 val32 |= val; 112 val32 |= (u32)val << 8; 116 val32 |= (u32)val << 16; 121 val32 |= (u32)val << 2 127 xgene_pcie_cfg_in32(void __iomem *addr, int offset, u32 *val) argument 132 xgene_pcie_cfg_in16(void __iomem *addr, int offset, u32 *val) argument 145 xgene_pcie_cfg_in8(void __iomem *addr, int offset, u32 *val) argument 216 xgene_pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) argument 247 xgene_pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) argument 286 u32 val; local 577 u32 val, lanes = 0, speed = 0; local [all...] |
/drivers/iio/gyro/ |
H A D | itg3200_core.c | 36 u8 reg_address, u8 val) 40 return i2c_smbus_write_byte_data(st->i2c, 0x80 | reg_address, val); 44 u8 reg_address, u8 *val) 52 *val = ret; 57 int *val) 82 *val = out; 89 int *val, int *val2, long info) 98 ret = itg3200_read_reg_s16(indio_dev, reg, val); 101 *val = 0; 109 *val 35 itg3200_write_reg_8(struct iio_dev *indio_dev, u8 reg_address, u8 val) argument 43 itg3200_read_reg_8(struct iio_dev *indio_dev, u8 reg_address, u8 *val) argument 56 itg3200_read_reg_s16(struct iio_dev *indio_dev, u8 lower_reg_address, int *val) argument 87 itg3200_read_raw(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, int *val, int *val2, long info) argument 132 itg3200_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) argument 206 u8 val; local 224 u8 val; local [all...] |
/drivers/media/i2c/ |
H A D | ml86v7667.c | 108 int val = i2c_smbus_read_byte_data(client, reg); local 109 if (val < 0) 110 return val; 112 val = (val & ~mask) | (data & mask); 113 return i2c_smbus_write_byte_data(client, reg, val); 125 SSEPL_LUMINANCE_MASK, ctrl->val); 129 CLC_CONTRAST_MASK, ctrl->val); 133 ctrl->val << ACCRC_CHROMA_SHIFT); 136 ret = ml86v7667_mask_set(client, HUE_REG, ~0, ctrl->val); 304 int val; local [all...] |
/drivers/video/backlight/ |
H A D | lm3533_bl.c | 59 u8 val; local 62 ret = lm3533_ctrlbank_get_brightness(&bl->cb, &val); 66 return val; 96 u8 val; local 101 ret = lm3533_read(bl->lm3533, LM3533_REG_CTRLBANK_AB_BCONF, &val); 106 enable = val & mask; 118 u8 val; local 128 val = mask; 130 val = 0; 132 ret = lm3533_update(bl->lm3533, LM3533_REG_CTRLBANK_AB_BCONF, val, 144 u8 val; local 170 u8 val; local 196 u8 val; local 211 u8 val; local [all...] |
/drivers/staging/comedi/drivers/ |
H A D | s526.c | 148 unsigned int val; local 234 val = (data[2] >> 16) & 0xffff; 235 outw(val, chan_iobase + REG_C0H); 238 val = data[2] & 0xffff; 239 outw(val, chan_iobase + REG_C0L); 243 val = data[3] & 0xffff; 244 outw(val, chan_iobase + REG_C0C); 272 val = (data[2] >> 16) & 0xffff; 273 outw(val, chan_iobase + REG_C0H); 276 val 475 unsigned int val = s->readback[chan]; local [all...] |
/drivers/clk/mmp/ |
H A D | clk-frac.c | 63 unsigned int val, num, den; local 65 val = readl_relaxed(factor->base); 68 num = (val >> masks->num_shift) & masks->num_mask; 71 den = (val >> masks->den_shift) & masks->den_mask; 87 unsigned long val; local 100 val = readl_relaxed(factor->base); 102 val &= ~(masks->num_mask << masks->num_shift); 103 val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift; 105 val &= ~(masks->den_mask << masks->den_shift); 106 val | [all...] |
/drivers/gpu/drm/i915/ |
H A D | dvo_sil164.c | 246 uint8_t val; local 248 sil164_readb(dvo, SIL164_FREQ_LO, &val); 249 DRM_DEBUG_KMS("SIL164_FREQ_LO: 0x%02x\n", val); 250 sil164_readb(dvo, SIL164_FREQ_HI, &val); 251 DRM_DEBUG_KMS("SIL164_FREQ_HI: 0x%02x\n", val); 252 sil164_readb(dvo, SIL164_REG8, &val); 253 DRM_DEBUG_KMS("SIL164_REG8: 0x%02x\n", val); 254 sil164_readb(dvo, SIL164_REG9, &val); 255 DRM_DEBUG_KMS("SIL164_REG9: 0x%02x\n", val); 256 sil164_readb(dvo, SIL164_REGC, &val); [all...] |
/drivers/hwmon/ |
H A D | smm665.c | 164 int rv, val; local 169 val = rv << 8; 173 val |= rv; 174 return val; 249 int i, val; local 254 val = smm665_read16(client, SMM665_MISC8_STATUS1); 255 if (unlikely(val < 0)) { 256 ret = ERR_PTR(val); 259 data->faults = val; 263 val 281 int val = 0; local 349 int val = 0; local 366 int val; local 633 int val; local [all...] |
/drivers/iio/dac/ |
H A D | mcp4922.c | 60 static int mcp4922_spi_write(struct mcp4922_state *state, u8 addr, u32 val) argument 62 state->mosi[1] = val & 0xff; 64 state->mosi[0] |= 0x30 | ((val >> 8) & 0x0f); 71 int *val, 79 *val = state->value[chan->channel]; 82 *val = state->vref_mv; 92 int val, 103 if (val > GENMASK(chan->scan_type.realbits-1, 0)) 105 val <<= chan->scan_type.shift; 106 state->value[chan->channel] = val; 69 mcp4922_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) argument 90 mcp4922_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) argument [all...] |
/drivers/usb/phy/ |
H A D | phy-am335x-control.c | 32 u32 val; local 50 val = readl(usb_ctrl->wkup); 53 val |= reg; 55 val &= ~reg; 57 writel(val, usb_ctrl->wkup); 64 u32 val; local 81 val = readl(usb_ctrl->phy_reg + reg); 83 val &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN); 84 val |= USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN; 86 val | [all...] |
/drivers/infiniband/hw/ipath/ |
H A D | ipath_stats.c | 54 u32 val, reg64 = 0; local 68 val = val64 == ~0ULL ? ~0U : 0; 71 val64 = val = ipath_read_creg32(dd, creg); 80 if (time_before(t0 + HZ, t1) && val == -1) { 92 if (val != dd->ipath_lastsword) { 93 dd->ipath_sword += val - dd->ipath_lastsword; 94 dd->ipath_lastsword = val; 98 if (val != dd->ipath_lastrword) { 99 dd->ipath_rword += val - dd->ipath_lastrword; 100 dd->ipath_lastrword = val; [all...] |
/drivers/power/ |
H A D | twl4030_madc_battery.c | 44 int val; local 53 val = twl4030_madc_conversion(&req); 54 if (val < 0) 55 return val; 114 union power_supply_propval *val) 123 val->intval = POWER_SUPPLY_STATUS_FULL; 126 val->intval = POWER_SUPPLY_STATUS_CHARGING; 128 val->intval = POWER_SUPPLY_STATUS_DISCHARGING; 132 val->intval = twl4030_madc_bat_get_voltage() * 1000; 135 val 112 twl4030_madc_bat_get_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) argument [all...] |
/drivers/staging/iio/accel/ |
H A D | adis16240_core.c | 37 s16 val = 0; local 42 this_attr->address, (u16 *)&val); 46 if (val & ADIS16240_ERROR_ACTIVE) 49 val = ((s16)(val << shift) >> shift); 50 return sprintf(buf, "%d\n", val); 82 int *val, int *val2, 94 ADIS16240_ERROR_ACTIVE, val); 99 *val = 4; 105 *val 80 adis16240_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) argument 155 adis16240_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) argument [all...] |
/drivers/vfio/pci/ |
H A D | vfio_pci_rdwr.c | 47 __le32 val; local 50 if (copy_from_user(&val, buf, 4)) 53 iowrite32(le32_to_cpu(val), io + off); 55 val = cpu_to_le32(ioread32(io + off)); 57 if (copy_to_user(buf, &val, 4)) 63 __le16 val; local 66 if (copy_from_user(&val, buf, 2)) 69 iowrite16(le16_to_cpu(val), io + off); 71 val = cpu_to_le16(ioread16(io + off)); 73 if (copy_to_user(buf, &val, 79 u8 val; local 98 u8 val = 0xFF; local [all...] |
/drivers/media/dvb-frontends/ |
H A D | nxt6000.c | 76 u8 val; local 78 val = nxt6000_readreg(state, OFDM_COR_CTL); 80 nxt6000_writereg(state, OFDM_COR_CTL, val & ~COREACT); 81 nxt6000_writereg(state, OFDM_COR_CTL, val | COREACT); 212 u8 val; local 228 val = nxt6000_readreg(state, RS_COR_STAT); 230 printk(" DATA DESCR LOCK: %d,", val & 0x01); 231 printk(" DATA SYNC LOCK: %d,", (val >> 1) & 0x01); 233 val = nxt6000_readreg(state, VIT_SYNC_STATUS); 235 printk(" VITERBI LOCK: %d,", (val >> [all...] |
/drivers/pci/ |
H A D | proc.c | 60 unsigned char val; local 61 pci_user_read_config_byte(dev, pos, &val); 62 __put_user(val, buf); 69 unsigned short val; local 70 pci_user_read_config_word(dev, pos, &val); 71 __put_user(cpu_to_le16(val), (__le16 __user *) buf); 78 unsigned int val; local 79 pci_user_read_config_dword(dev, pos, &val); 80 __put_user(cpu_to_le32(val), (__le32 __user *) buf); 87 unsigned short val; local 96 unsigned char val; local 133 unsigned char val; local 142 __le16 val; local 151 __le32 val; local 160 __le16 val; local 169 unsigned char val; local [all...] |
/drivers/clk/spear/ |
H A D | clk-vco-pll.c | 149 unsigned long flags = 0, val; local 157 val = readl_relaxed(pll->vco->cfg_reg); 158 val &= ~(PLL_DIV_P_MASK << PLL_DIV_P_SHIFT); 159 val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT; 160 writel_relaxed(val, pll->vco->cfg_reg); 197 unsigned int num = 2, den = 0, val, mode = 0; local 204 val = readl_relaxed(vco->cfg_reg); 209 den = (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK; 214 num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK; 217 num *= (val >> PLL_DITH_FDBK_M_SHIF 235 unsigned long flags = 0, val; local [all...] |
/drivers/media/i2c/m5mols/ |
H A D | m5mols_controls.c | 191 bool af_lock = ctrl->val & V4L2_LOCK_FOCUS; 194 if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE) { 195 bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE; 203 if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE) 204 && info->auto_wb->val) { 205 bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE; 216 if ((ctrl->val ^ ctrl->cur.val) 279 m5mols_set_white_balance(struct m5mols_info *info, int val) argument 317 m5mols_set_saturation(struct m5mols_info *info, int val) argument 326 m5mols_set_color_effect(struct m5mols_info *info, int val) argument 390 m5mols_set_stabilization(struct m5mols_info *info, int val) argument [all...] |
/drivers/net/ieee802154/ |
H A D | mrf24j40.c | 125 static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val) argument 147 *val = devrec->buf[1]; 184 static int write_long_reg(struct mrf24j40 *devrec, u16 reg, u8 val) argument 202 devrec->buf[2] = val; 337 u8 val; local 349 ret = read_short_reg(devrec, REG_TXNCON, &val); 352 val |= 0x1; 355 val |= 0x4; 356 write_short_reg(devrec, REG_TXNCON, val); 371 ret = read_short_reg(devrec, REG_TXSTAT, &val); 396 u8 val; local 413 u8 val; local 429 u8 val; local 507 u8 val; local 534 u8 val; local 617 u8 val; local [all...] |
/drivers/media/platform/davinci/ |
H A D | isif.c | 156 static inline void regw(u32 val, u32 offset) argument 158 __raw_writel(val, isif_cfg.base_addr + offset); 162 static inline u32 reg_modify(u32 mask, u32 val, u32 offset) argument 164 u32 new_val = (regr(offset) & ~mask) | (val & mask); 170 static inline void regw_lin_tbl(u32 val, u32 offset, int i) argument 173 __raw_writel(val, isif_cfg.linear_tbl0_addr + offset); 175 __raw_writel(val, isif_cfg.linear_tbl1_addr + offset); 212 u32 val; local 215 val = (cul->hcpat_even << CULL_PAT_EVEN_LINE_SHIFT) | cul->hcpat_odd; 216 regw(val, CUL 230 u32 val; local 326 u32 val; local 388 u32 val, i; local 416 u32 val, count, retries = loops_per_jiffy / (4000/HZ); local 550 u32 val; local [all...] |
/drivers/char/ipmi/ |
H A D | ipmi_devintf.c | 375 struct ipmi_cmdspec val; local 377 if (copy_from_user(&val, arg, sizeof(val))) { 382 rv = ipmi_register_for_cmd(priv->user, val.netfn, val.cmd, 389 struct ipmi_cmdspec val; local 391 if (copy_from_user(&val, arg, sizeof(val))) { 396 rv = ipmi_unregister_for_cmd(priv->user, val.netfn, val 403 struct ipmi_cmdspec_chans val; local 417 struct ipmi_cmdspec_chans val; local 431 int val; local 445 unsigned int val; local 458 unsigned int val; local 476 unsigned int val; local 489 unsigned int val; local 507 struct ipmi_channel_lun_address_set val; local 520 struct ipmi_channel_lun_address_set val; local 540 struct ipmi_channel_lun_address_set val; local 553 struct ipmi_channel_lun_address_set val; local [all...] |
/drivers/mfd/ |
H A D | menelaus.c | 186 int val = i2c_smbus_write_byte_data(the_menelaus->client, reg, value); local 188 if (val < 0) { 190 return val; 198 int val = i2c_smbus_read_byte_data(the_menelaus->client, reg); local 200 if (val < 0) 203 return val; 300 int ret, val; local 310 val = ret; 313 val |= MCT_CTRL1_S1_CMD_OD; 315 val 351 int ret, val; local 459 u16 val; member in struct:menelaus_vtg_value 465 int val, ret; local 537 int val, ret; local 560 int fval, rval, val, ret; local 612 int val; local 641 int val; local 683 int val; local 719 int val; local 749 int val; local 767 menelaus_set_regulator_sleep(int enable, u32 val) argument [all...] |
/drivers/mmc/host/ |
H A D | sdhci-esdhc-imx.c | 213 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) argument 218 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 225 u32 val = readl(host->ioaddr + reg); local 228 u32 fsl_prss = val; 230 val = fsl_prss & 0x000FFFFF; 232 val |= (fsl_prss & 0x0F000000) >> 4; 234 val |= (fsl_prss & 0x00800000) << 1; 238 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 240 val &= 0xffff0000; 249 if (val 296 esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) argument 353 u32 val; local 408 esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) argument 508 esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) argument 597 u32 temp, val; local 688 esdhc_prepare_tuning(struct sdhci_host *host, u32 val) argument [all...] |