Searched refs:select (Results 1 - 25 of 33) sorted by last modified time

12

/arch/sh/lib/
H A D	memcpy-sh4.S	260 ! Now select the appropriate bulk transfer code based on relative
/arch/xtensa/include/asm/
H A D	coprocessor.h	40 xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT variable 47 xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT variable 59 xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT variable 66 xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT variable
/arch/xtensa/variants/dc232b/include/variant/
H A D	tie-asm.h	37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 47 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 59 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 65 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 78 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 80 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 88 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 100 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 106 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select [all...]
/arch/xtensa/variants/dc233c/include/variant/
H A D	tie-asm.h	71 * select Select what category(ies) of registers to store, as a bitmask 74 * category is selected here that is not in <select>, space for 77 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 80 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 90 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 102 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 135 * select Select what category(ies) of registers to load, as a bitmask 138 * category is selected here that is not in <select>, space for 141 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 144 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) [all...]
/arch/xtensa/variants/fsf/include/variant/
H A D	tie-asm.h	37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 52 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 54 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
/arch/xtensa/variants/s6000/include/variant/
H A D	tie-asm.h	37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 52 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 54 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 74 .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 76 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 108 .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 110 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 144 .macro xchal_cp6_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 146 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select [all...]
/arch/cris/arch-v10/kernel/
H A D	debugport.c	160 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser2, select); 168 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser3, select);
H A D	head.S	420 or.d IO_STATE (R_GEN_CONFIG, ser2, select),$r0
H A D	io_interface_mux.c	700 SETS(gens, R_GEN_CONFIG, ser2, select); 703 SETS(gens, R_GEN_CONFIG, ser3, select); 712 SETS(gens, R_GEN_CONFIG, ser3, select); 717 SETS(gens, R_GEN_CONFIG, mio, select); 720 SETS(gens, R_GEN_CONFIG, mio_w, select); 723 SETS(gens, R_GEN_CONFIG, par0, select); 726 SETS(gens, R_GEN_CONFIG, par1, select); 729 SETS(gens, R_GEN_CONFIG, par0, select); 730 SETS(gens, R_GEN_CONFIG, par_w, select); 733 SETS(gens, R_GEN_CONFIG, scsi0, select); [all...]
/arch/cris/arch-v10/mm/
H A D	fault.c	42 int select; local 58 select = *R_TLB_SELECT; 64 index = IO_EXTRACT(R_TLB_SELECT, index, select); 90 *R_TLB_SELECT = select;
/arch/cris/arch-v32/kernel/
H A D	head.S	63 ;; Note; 3 cycles is needed for a bank-select to take effect. Further;
/arch/m32r/mm/
H A D	mmu.S	102 ;; select TLB entry
/arch/m68k/coldfire/
H A D	device.c	311 .select = mcf_cs_select,
/arch/m68k/fpsp040/
H A D	res_func.S	117 andib #0x3b,%d0 |isolate bits to select inst 420 andib #0x3b,%d0 |isolate bits to select inst
/arch/m68k/include/asm/
H A D	mcfqspi.h	25 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver 28 * @select: output the signals to select the device. Can not be NULL. 33 * platform data for each QSPI master controller. Only the select and 39 void (*select)(struct mcfqspi_cs_control *, u8, bool); member in struct:mcfqspi_cs_control 47 * @cs_control: platform dependent chip select control.
/arch/mips/cavium-octeon/executive/
H A D	cvmx-helper-jtag.c	95 jtgd.s.select = 1 << qlm; 139 jtgd.s.select = 1 << qlm;
/arch/mips/include/asm/octeon/
H A D	cvmx-ciu-defs.h	8309 uint64_t select:5; member in struct:cvmx_ciu_qlm_jtgd::cvmx_ciu_qlm_jtgd_s 8317 uint64_t select:5; 8330 uint64_t select:2; member in struct:cvmx_ciu_qlm_jtgd::cvmx_ciu_qlm_jtgd_cn52xx 8338 uint64_t select:2; 8352 uint64_t select:4; member in struct:cvmx_ciu_qlm_jtgd::cvmx_ciu_qlm_jtgd_cn56xx 8360 uint64_t select:4; 8390 uint64_t select:3; member in struct:cvmx_ciu_qlm_jtgd::cvmx_ciu_qlm_jtgd_cn61xx 8398 uint64_t select:3;
/arch/parisc/kernel/
H A D	syscall_table.S	226 /* it is POSSIBLE that select will be OK because even though fd_set 228 ENTRY_COMP(select)
/arch/arm/boot/compressed/
H A D	head.S	20 * Please select one of the following when turning on debugging. 1110 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 1141 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
/arch/arm/boot/dts/
H A D	armada-xp-lenovo-ix4-300d.dts	69 select_button_pin: select-button-pin { 201 select-button {
H A D	kirkwood-openrd.dtsi	43 pmx_select28: pmx-select-uart-sd { 51 pmx_select34: pmx-select-rs232-rs484 {
/arch/arm/crypto/
H A D	aes-armv4.S	34 @ A little glue here to select the correct code below for the ARM CPU
/arch/arm/kernel/
H A D	fiqasm.S	28 msr cpsr_c, r2 @ select FIQ mode 41 msr cpsr_c, r2 @ select FIQ mode
/arch/arm/mach-at91/
H A D	gpio.c	112 u8 select; local 116 select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask); 117 select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1); 118 ret = 'A' + select;
/arch/arm/mach-s3c24xx/
H A D	dma-s3c2410.c	107 .select = s3c2410_dma_select,

Completed in 823 milliseconds

12

Indexes created Tue Oct 13 23:51:09 CEST 2015