/drivers/media/platform/s5p-jpeg/ |
H A D | jpeg-hw-exynos3250.c | 26 writel(1, regs + EXYNOS3250_SW_RESET); 38 writel(1, regs + EXYNOS3250_JPGDRI); 44 writel(0, regs + EXYNOS3250_JPGDRI); 49 writel(EXYNOS3250_POWER_ON, regs + EXYNOS3250_JPGCLKCON); 54 writel(((EXYNOS3250_DMA_MO_COUNT << EXYNOS3250_WDMA_ISSUE_NUM_SHIFT) & 69 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); 120 writel(reg, regs + EXYNOS3250_JPGCMOD); 132 writel(reg, regs + EXYNOS3250_JPGCMOD); 146 writel(reg, regs + EXYNOS3250_JPGMOD); 168 writel(re [all...] |
H A D | jpeg-hw-s5p.c | 24 writel(1, regs + S5P_JPG_SW_RESET); 35 writel(S5P_POWER_ON, regs + S5P_JPGCLKCON); 51 writel(reg, regs + S5P_JPGCMOD); 63 writel(reg, regs + S5P_JPGCMOD); 78 writel(reg, regs + S5P_JPGMOD); 93 writel(reg, regs + S5P_JPGMOD); 108 writel(reg, regs + S5P_JPGDRI_U); 113 writel(reg, regs + S5P_JPGDRI_L); 123 writel(reg, regs + S5P_JPG_QTBL); 134 writel(re [all...] |
H A D | jpeg-hw-exynos4.c | 24 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); 28 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); 38 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | 42 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | 118 writel(reg, base + EXYNOS4_IMG_FMT_REG); 149 writel(reg, base + EXYNOS4_IMG_FMT_REG); 154 writel(EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); 182 writel(reg | EXYNOS4_HUF_TBL_EN, 185 writel(reg & ~EXYNOS4_HUF_TBL_EN, 196 writel(re [all...] |
/drivers/video/fbdev/ |
H A D | wmt_ge_rops.c | 67 writel(p->var.bits_per_pixel == 32 ? 3 : 69 writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF); 70 writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF); 71 writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF); 72 writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF); 73 writel(rect->dx, regbase + GE_DESTAREAX_OFF); 74 writel(rect->dy, regbase + GE_DESTAREAY_OFF); 75 writel(rect->width - 1, regbase + GE_DESTAREAW_OFF); 76 writel(rect->height - 1, regbase + GE_DESTAREAH_OFF); 78 writel(pa [all...] |
H A D | w100fb.c | 133 writel(param, remapped_regs + regs); 297 writel(W100_FB_BASE, remapped_regs + mmDST_OFFSET); 298 writel(par->xres, remapped_regs + mmDST_PITCH); 299 writel(W100_FB_BASE, remapped_regs + mmSRC_OFFSET); 300 writel(par->xres, remapped_regs + mmSRC_PITCH); 303 writel(0, remapped_regs + mmSC_TOP_LEFT); 304 writel((par->yres << 16) | par->xres, remapped_regs + mmSC_BOTTOM_RIGHT); 305 writel(0x1fff1fff, remapped_regs + mmSRC_SC_BOTTOM_RIGHT); 315 writel(dp_cntl.val, remapped_regs + mmDP_CNTL); 332 writel(gm [all...] |
/drivers/gpu/drm/exynos/ |
H A D | exynos_dp_reg.c | 34 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 38 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 48 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 62 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); 70 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); 73 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); 76 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); 80 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); 84 writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL); 90 writel(INT_POL [all...] |
/drivers/net/ethernet/chelsio/cxgb/ |
H A D | tp.c | 31 writel(val, ap->regs + A_TP_IN_CONFIG); 32 writel(F_TP_OUT_CSPI_CPL | 36 writel(V_IP_TTL(64) | 46 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR | 77 writel(0xffffffff, 79 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP, 85 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); 86 writel(tp_intr | F_PL_INTR_TP, 98 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); 99 writel(tp_int [all...] |
H A D | espi.c | 65 writel(V_WRITE_DATA(wr_data) | 71 writel(0, adapter->regs + A_ESPI_GOSTAT); 92 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); 111 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST, 129 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); 130 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); 136 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); 137 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); 144 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); 145 writel(pl_int [all...] |
/drivers/video/fbdev/via/ |
H A D | accel.c | 48 writel(gemode, engine + VIA_REG_GEMODE); 105 writel(tmp, engine + 0x08); 114 writel(tmp, engine + 0x0C); 122 writel(tmp, engine + 0x10); 125 writel(fg_color, engine + 0x18); 128 writel(bg_color, engine + 0x1C); 138 writel(tmp, engine + 0x30); 147 writel(tmp, engine + 0x34); 159 writel(tmp, engine + 0x38); 172 writel(ge_cm [all...] |
/drivers/clocksource/ |
H A D | timer-u300.c | 204 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, 207 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, 213 writel(cevdata->ticks_per_jiffy, 219 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS, 222 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, 225 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, 236 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, 239 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, 245 writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC); 247 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHO [all...] |
H A D | vt8500_timer.c | 58 writel(3, regbase + TIMER_CTRL_VAL); 81 writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); 86 writel(1, regbase + TIMER_IER_VAL); 101 writel(readl(regbase + TIMER_CTRL_VAL) | 1, 103 writel(0, regbase + TIMER_IER_VAL); 119 writel(0xf, regbase + TIMER_STATUS_VAL); 149 writel(1, regbase + TIMER_CTRL_VAL); 150 writel(0xf, regbase + TIMER_STATUS_VAL); 151 writel(~0, regbase + TIMER_MATCH_VAL);
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/drivers/net/ethernet/stmicro/stmmac/ |
H A D | stmmac_hwtstamp.c | 33 writel(data, ioaddr + PTP_TCR); 51 writel(data, ioaddr + PTP_SSIR); 59 writel(sec, ioaddr + PTP_STSUR); 60 writel(nsec, ioaddr + PTP_STNSUR); 64 writel(value, ioaddr + PTP_TCR); 84 writel(addend, ioaddr + PTP_TAR); 88 writel(value, ioaddr + PTP_TCR); 109 writel(sec, ioaddr + PTP_STSUR); 110 writel(((add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec), 115 writel(valu [all...] |
H A D | dwmac_lib.c | 32 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); 37 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 42 writel(0, ioaddr + DMA_INTR_ENA); 49 writel(value, ioaddr + DMA_CONTROL); 56 writel(value, ioaddr + DMA_CONTROL); 63 writel(value, ioaddr + DMA_CONTROL); 70 writel(value, ioaddr + DMA_CONTROL); 209 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); 217 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); 232 writel(dat [all...] |
/drivers/scsi/bfa/ |
H A D | bfa_ioc_ct.c | 73 writel(1, ioc->ioc_regs.ioc_usage_reg); 75 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); 76 writel(0, ioc->ioc_regs.ioc_fail_sync); 95 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); 104 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); 106 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); 124 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); 128 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); 138 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); 139 writel(__FW_INIT_HALT_ [all...] |
H A D | bfa_ioc_cb.c | 121 writel(~0U, ioc->ioc_regs.err_set); 234 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate); 235 writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate); 255 writel(1, ioc->ioc_regs.ioc_sem_reg); 267 writel((r32 | join_pos), ioc->ioc_regs.ioc_fwstate); 276 writel((r32 & ~join_pos), ioc->ioc_regs.ioc_fwstate); 285 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), 302 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), 378 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG)); 381 writel((BFI_IOC_UNINI [all...] |
/drivers/video/fbdev/geode/ |
H A D | display_gx1.c | 90 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); 97 writel(tcfg, par->dc_regs + DC_TIMING_CFG); 104 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); 108 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); 114 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); 135 writel(0, par->dc_regs + DC_FB_ST_OFFSET); 138 writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA); 139 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, 166 writel(val, par->dc_regs + DC_H_TIMING_1); 168 writel(va [all...] |
/drivers/irqchip/ |
H A D | irq-sun4i.c | 48 writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); 59 writel(val & ~(1 << irq_off), 71 writel(val | (1 << irq_off), 106 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0)); 107 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1)); 108 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2)); 111 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0)); 112 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1)); 113 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2)); 116 writel( [all...] |
/drivers/gpu/drm/sti/ |
H A D | sti_vtg.c | 112 writel(1, vtg->regs + VTG_DRST_AUTOC); 123 writel(mode->htotal, vtg->regs + VTG_CLKLN); 124 writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN); 128 writel(tmp, vtg->regs + VTG_VID_TFO); 129 writel(tmp, vtg->regs + VTG_VID_BFO); 133 writel(tmp, vtg->regs + VTG_VID_TFS); 134 writel(tmp, vtg->regs + VTG_VID_BFS); 138 writel(tmp, vtg->regs + VTG_H_HD_1); 139 writel(tmp, vtg->regs + VTG_H_HD_2); 143 writel(tm [all...] |
H A D | sti_vid.c | 53 writel(val, vid->regs + VID_CTL); 68 writel((ydo << 16) | xdo, vid->regs + VID_VPO); 69 writel((yds << 16) | xds, vid->regs + VID_VPS); 81 writel(val, vid->regs + VID_CTL); 99 writel(VID_CTL_PSI_ENABLE | VID_CTL_IGNORE, vid->regs + VID_CTL); 102 writel(VID_ALP_OPAQUE, vid->regs + VID_ALP); 105 writel(VID_MPR0_BT709, vid->regs + VID_MPR0); 106 writel(VID_MPR1_BT709, vid->regs + VID_MPR1); 107 writel(VID_MPR2_BT709, vid->regs + VID_MPR2); 108 writel(VID_MPR3_BT70 [all...] |
/drivers/net/ethernet/brocade/bna/ |
H A D | bfa_ioc_ct.c | 139 writel(1, ioc->ioc_regs.ioc_usage_reg); 141 writel(0, ioc->ioc_regs.ioc_fail_sync); 165 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); 190 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); 199 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); 200 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); 427 writel(r32, rb + FNC_PERS_REG); 437 writel(1, ioc->ioc_regs.lpu_read_stat); 460 writel(r32 & __MSIX_VT_OFST_, 465 writel(__MSIX_VT_NUMVT [all...] |
/drivers/power/reset/ |
H A D | sun6i-reboot.c | 39 writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG); 42 writel(SUN6I_WATCHDOG1_CONFIG_RESTART, 46 writel(SUN6I_WATCHDOG1_MODE_ENABLE, 50 writel(SUN6I_WATCHDOG1_CTRL_RESTART, 55 writel(SUN6I_WATCHDOG1_MODE_ENABLE,
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/drivers/net/ethernet/samsung/sxgbe/ |
H A D | sxgbe_dma.c | 41 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); 57 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); 61 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); 65 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); 69 writel(upper_32_bits(dma_tx), 71 writel(lower_32_bits(dma_tx), 74 writel(upper_32_bits(dma_rx), 76 writel(lower_32_bits(dma_rx), 84 writel(lower_32_bits(dma_addr), 88 writel(lower_32_bit [all...] |
/drivers/media/platform/exynos-gsc/ |
H A D | gsc-regs.c | 20 writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET); 47 writel(cfg, dev->regs + GSC_IRQ); 59 writel(cfg, dev->regs + GSC_IRQ); 71 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_Y_MASK); 72 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CB_MASK); 73 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CR_MASK); 85 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_Y_MASK); 86 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CB_MASK); 87 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CR_MASK); 95 writel(add [all...] |
/drivers/media/platform/exynos4-is/ |
H A D | fimc-lite-reg.c | 30 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); 40 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); 47 writel(cfg, dev->regs + FLITE_REG_CISTATUS); 61 writel(cfg, dev->regs + FLITE_REG_CISTATUS2); 83 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); 90 writel(cfg, dev->regs + FLITE_REG_CIIMGCPT); 97 writel(cfg, dev->regs + FLITE_REG_CIIMGCPT); 111 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); 150 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); 157 writel(cf [all...] |
/drivers/video/fbdev/exynos/ |
H A D | exynos_mipi_dsi_lowlevel.c | 40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); 51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); 62 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); 90 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK); 100 writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); 104 writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); 113 writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR); 128 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); 139 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); 145 writel(re [all...] |