Searched refs:clock (Results 1 - 25 of 324) sorted by relevance

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/drivers/video/via/
H A Dvia_clock.c23 * clock and PLL management functions
274 printk(KERN_INFO "Using undocumented set clock state.\n%s", via_slap);
279 printk(KERN_INFO "Using undocumented set clock source.\n%s", via_slap);
292 void via_clock_init(struct via_clock *clock, int gfx_chip) argument
297 clock->set_primary_clock_state = dummy_set_clock_state;
298 clock->set_primary_clock_source = dummy_set_clock_source;
299 clock->set_primary_pll_state = dummy_set_pll_state;
300 clock->set_primary_pll = cle266_set_primary_pll;
302 clock->set_secondary_clock_state = dummy_set_clock_state;
303 clock
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/drivers/mmc/host/
H A Dsdhci-esdhc.h45 static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock) argument
56 if (clock == 0)
59 while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
62 while (host->max_clk / pre_div / div > clock && div < 16)
65 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
66 clock, host->max_clk / pre_div / div);
78 host->clock = clock;
H A Dsdhci-cns3xxx.c27 static void sdhci_cns3xxx_set_clock(struct sdhci_host *host, unsigned int clock) argument
34 if (clock == host->clock)
39 if (clock == 0)
42 while (host->max_clk / div > clock) {
55 dev_dbg(dev, "desired SD clock: %d, actual: %d\n",
56 clock, host->max_clk / div);
70 dev_warn(dev, "clock is unstable");
80 host->clock = clock;
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H A Dsdhci-of-esdhc.c108 return pltfm_host->clock;
115 return pltfm_host->clock / 256 / 16;
118 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) argument
120 /* Workaround to reduce the clock frequency for p1010 esdhc */
122 if (clock > 20000000)
123 clock -= 5000000;
124 if (clock > 40000000)
125 clock -= 5000000;
128 /* Set the clock */
129 esdhc_set_clock(host, clock);
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/drivers/media/video/s5p-mfc/
H A Ds5p_mfc_pm.c43 mfc_err("Failed to get clock-gating control\n");
50 mfc_err("Failed to preapre clock-gating control\n");
54 pm->clock = clk_get(&dev->plat_dev->dev, MFC_CLKNAME);
55 if (IS_ERR(pm->clock)) {
56 mfc_err("Failed to get MFC clock\n");
57 ret = PTR_ERR(pm->clock);
61 ret = clk_prepare(pm->clock);
63 mfc_err("Failed to prepare MFC clock\n");
77 clk_put(pm->clock);
90 clk_unprepare(pm->clock);
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/drivers/net/phy/
H A Ddp83640.c88 struct dp83640_clock *clock; member in struct:dp83640_private
113 /* we create one clock instance per MII bus */
127 /* reference to our PTP hardware clock */
154 "The address of the PHY to use for the ancillary clock features");
179 if (dp83640->clock->page != page) {
181 dp83640->clock->page = page;
194 if (dp83640->clock->page != page) {
196 dp83640->clock->page = page;
251 static void periodic_output(struct dp83640_clock *clock, argument
254 struct dp83640_private *dp83640 = clock
310 struct dp83640_clock *clock = local
343 struct dp83640_clock *clock = local
364 struct dp83640_clock *clock = local
389 struct dp83640_clock *clock = local
406 struct dp83640_clock *clock = local
515 recalibrate(struct dp83640_clock *clock) argument
842 struct dp83640_clock *clock; local
863 dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) argument
888 choose_this_phy(struct dp83640_clock *clock, struct phy_device *phydev) argument
900 dp83640_clock_get(struct dp83640_clock *clock) argument
913 struct dp83640_clock *clock = NULL, *tmp; local
940 dp83640_clock_put(struct dp83640_clock *clock) argument
947 struct dp83640_clock *clock; local
1007 struct dp83640_clock *clock; local
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/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c180 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
182 static void i8xx_clock(int refclk, struct psb_intel_clock_t *clock) argument
184 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
185 clock->p = clock->p1 * clock->p2;
186 clock->vco = refclk * clock
192 i9xx_clock(int refclk, struct psb_intel_clock_t *clock) argument
200 psb_intel_clock(struct drm_device *dev, int refclk, struct psb_intel_clock_t *clock) argument
232 psb_intel_PLL_is_valid(struct drm_crtc *crtc, struct psb_intel_clock_t *clock) argument
273 struct psb_intel_clock_t clock; local
609 struct psb_intel_clock_t clock; local
1121 struct psb_intel_clock_t clock; local
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H A Dcdv_intel_display.c214 * DPLL reference clock is on in the DPLL control register, but before
219 struct cdv_intel_clock_t *clock)
248 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
264 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
266 if (clock->vco < 2250000) {
269 } else if (clock->vco < 2750000) {
272 } else if (clock->vco < 3300000) {
288 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
289 switch (clock->p2) {
303 DRM_ERROR("Bad P2 clock
218 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, struct cdv_intel_clock_t *clock) argument
387 cdv_intel_clock(struct drm_device *dev, int refclk, struct cdv_intel_clock_t *clock) argument
398 cdv_intel_PLL_is_valid(struct drm_crtc *crtc, const struct cdv_intel_limit_t *limit, struct cdv_intel_clock_t *clock) argument
424 struct cdv_intel_clock_t clock; local
728 struct cdv_intel_clock_t clock; local
1287 i8xx_clock(int refclk, struct cdv_intel_clock_t *clock) argument
1303 struct cdv_intel_clock_t clock; local
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H A Doaktrail_crtc.c112 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
113 static void oaktrail_clock(int refclk, struct oaktrail_clock_t *clock) argument
115 clock->dot = (refclk * clock->m) / (14 * clock->p1);
118 static void mrstPrintPll(char *prefix, struct oaktrail_clock_t *clock) argument
121 prefix, clock->dot, clock->m, clock->p1);
125 * Returns a set of divisors for the desired target clock wit
132 struct oaktrail_clock_t clock; local
307 struct oaktrail_clock_t clock; local
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/drivers/video/vermilion/
H A Dcr_pll.c100 static int crvml_nearest_index(const struct vml_sys *sys, int clock) argument
107 cur_diff = clock - crvml_clocks[0];
110 diff = clock - crvml_clocks[i];
120 static int crvml_nearest_clock(const struct vml_sys *sys, int clock) argument
122 return crvml_clocks[crvml_nearest_index(sys, clock)];
125 static int crvml_set_clock(struct vml_sys *sys, int clock) argument
131 index = crvml_nearest_index(sys, clock);
133 if (crvml_clocks[index] != clock)
/drivers/video/matrox/
H A Dmatroxfb_maven.h16 unsigned int clock; member in struct:i2c_bit_adapter::__anon5848
/drivers/ptp/
H A DKconfig2 # PTP clock support configuration
5 menu "PTP clock support"
7 comment "Enable Device Drivers -> PPS to see the PTP clock options."
11 tristate "PTP clock support"
24 devices. If you want to use a PTP clock, then you should
25 also enable at least one clock driver as well.
31 tristate "Freescale eTSEC as PTP clock"
36 clock. This clock is only useful if your PTP programs are
44 tristate "Intel IXP46x as PTP clock"
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H A Dptp_private.h2 * PTP 1588 clock support - private declarations for the core module.
26 #include <linux/posix-clock.h>
42 struct posix_clock clock; member in struct:ptp_clock
51 int defunct; /* tells readers to go away when clock is being removed */
H A Dptp_clock.c2 * PTP 1588 clock support
26 #include <linux/posix-clock.h>
100 /* posix clock implementation */
111 struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
117 struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
123 struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
169 struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
173 /* Remove the clock from the bit map. */
191 /* Find a free clock slot and reserve it. */
200 /* Initialize a clock structur
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/drivers/ata/
H A Dpata_opti.c104 * are two tables depending on the hardware clock speed.
110 int clock; local
126 clock = ioread16(regio + 5) & 1;
133 addr = addr_timing[clock][pio];
136 u8 pair_addr = addr_timing[clock][pair->pio_mode - XFER_PIO_0];
143 opti_write_reg(ap, data_rec_timing[clock][pio], READ_REG);
144 opti_write_reg(ap, data_rec_timing[clock][pio], WRITE_REG);
H A Dpata_pdc202xx_old.c170 * In UDMA3 or higher we have to clock switch for the duration of the
185 void __iomem *clock = master + 0x11; local
192 iowrite8(ioread8(clock) | sel66, clock);
194 iowrite8(ioread8(clock) & ~sel66, clock); local
220 * After a DMA completes we need to put the clock back to 33MHz for
234 /* The clock bits are in the same register for both channels */
236 void __iomem *clock = master + 0x11; local
242 iowrite8(ioread8(clock)
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/drivers/pcmcia/
H A Dpxa2xx_base.c109 * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
117 static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
121 val = ((pxa2xx_mcxx_setup(speed, clock)
123 | ((pxa2xx_mcxx_asst(speed, clock)
125 | ((pxa2xx_mcxx_hold(speed, clock)
133 static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
137 val = ((pxa2xx_mcxx_setup(speed, clock)
139 | ((pxa2xx_mcxx_asst(speed, clock)
141 | ((pxa2xx_mcxx_hold(speed, clock)
149 static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
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/drivers/media/dvb/frontends/
H A Ddrxd.h39 u32 clock; member in struct:drxd_config
/drivers/mfd/
H A Ddb8500-prcmu.c699 * prcmu_config_clkout - Configure one of the programmable clock outputs.
701 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
704 * Configures one of the programmable clock outputs (CLKOUTs).
1082 pr_err("prcmu: Bad clock divider %d in %s\n",
1238 static int request_pll(u8 clock, bool enable) argument
1242 if (clock == PRCMU_PLLSOC0)
1243 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1244 else if (clock == PRCMU_PLLSOC1)
1245 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1255 writeb(clock, (tcdm_bas
1437 request_clock(u8 clock, bool enable) argument
1465 request_sga_clock(u8 clock, bool enable) argument
1565 db8500_prcmu_request_clock(u8 clock, bool enable) argument
1624 clock_rate(u8 clock) argument
1697 prcmu_clock_rate(u8 clock) argument
1749 round_clock_rate(u8 clock, unsigned long rate) argument
1846 prcmu_round_clock_rate(u8 clock, unsigned long rate) argument
1860 set_clock_rate(u8 clock, unsigned long rate) argument
1985 prcmu_set_clock_rate(u8 clock, unsigned long rate) argument
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/drivers/scsi/
H A Dsim710.c100 int irq, int clock, int differential, int scsi_id)
107 printk(KERN_NOTICE "sim710: irq = %d, clock = %d, base = 0x%lx, scsi_id = %d\n",
108 irq, clock, base_addr, scsi_id);
124 hostdata->clock = clock;
202 int clock; local
245 clock = 50;
254 clock = 50;
264 return sim710_probe_common(dev, base, irq_vector, clock,
99 sim710_probe_common(struct device *dev, unsigned long base_addr, int irq, int clock, int differential, int scsi_id) argument
H A Dzalon.c52 * future. The clock = (int) pdc_result[16] does not look correct to
57 /* poke SCSI clock out of iodc data */
65 int clock, status;
69 clock = (int) pdc_result[16];
72 clock = defaultclock;
75 printk(KERN_DEBUG "%s: SCSI clock %d\n", __func__, clock);
76 return clock;
/drivers/net/can/cc770/
H A Dcc770_platform.c38 * bosch,external-clock-frequency = <16000000>;
85 prop = of_get_property(np, "bosch,external-clock-frequency",
91 priv->can.clock.freq = clkext;
93 /* The system clock may not exceed 10 MHz */
94 if (priv->can.clock.freq > 10000000) {
96 priv->can.clock.freq /= 2;
99 /* The memory clock may not exceed 8 MHz */
100 if (priv->can.clock.freq > 8000000)
103 if (of_get_property(np, "bosch,divide-memory-clock", NULL))
119 prop = of_get_property(np, "bosch,clock
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/drivers/net/ethernet/freescale/fs_enet/
H A Dmii-fec.c112 int ret = -ENOMEM, clock, speed; local
144 clock = get_bus_freq(ofdev->dev.of_node);
145 if (!clock) {
146 /* Use maximum divider if clock is unknown */
147 dev_warn(&ofdev->dev, "could not determine IPS clock\n");
148 clock = 0x3F * 5000000;
151 clock = ppc_proc_freq;
154 * Scale for a MII clock <= 2.5 MHz
157 speed = (clock + 4999999) / 5000000;
161 "MII clock (
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/drivers/ide/
H A Dpdc202xx_old.c118 * clock for UDMA 3/4/5 mode operation when necessary.
122 * It may also be possible to leave the 66MHz clock on
128 u8 clock = inb(clock_reg); local
130 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
136 u8 clock = inb(clock_reg); local
138 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
156 u8 clock = inb(high_16 + 0x11); local
158 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
174 u8 clock = 0; local
177 clock
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/drivers/input/touchscreen/
H A Ds3c2410_ts.c67 * @clock: The clock for the adc.
80 struct clk *clock; member in struct:s3c2410ts
262 ts.clock = clk_get(dev, "adc");
263 if (IS_ERR(ts.clock)) {
264 dev_err(dev, "cannot get adc clock source\n");
268 clk_enable(ts.clock);
358 clk_put(ts.clock);
373 clk_disable(ts.clock);
374 clk_put(ts.clock);
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