/external/clang/test/Sema/ |
H A D | block-call.c | 3 int (*FP)(); variable 7 int (*FPL) (int) = FP; // C doesn't consider this an error.
|
/external/clang/test/SemaCXX/ |
H A D | block-call.cpp | 3 int (*FP)(); variable 7 int (*FPL) (int) = FP; // expected-error {{cannot initialize a variable of type 'int (*)(int)' with an lvalue of type 'int (*)()'}}
|
H A D | explicit.cpp | 163 struct FP { struct 170 FP fp;
|
/external/libffi/src/sparc/ |
H A D | v9.S | 135 #define FP %fp+STACK_BIAS define 151 stx %i0, [FP+128+0] 152 stx %i1, [FP+128+8] 153 stx %i2, [FP+128+16] 154 stx %i3, [FP+128+24] 155 stx %i4, [FP+128+32] 156 stx %i5, [FP+128+40] 159 std %f0, [FP-128] 160 std %f2, [FP-120] 161 std %f4, [FP [all...] |
/external/clang/test/CodeGen/ |
H A D | struct-init.c | 37 void (*FP)(struct fp_struct_bar); member in struct:fp_struct_foo
|
H A D | pointer-arithmetic.c | 10 typedef void (*FP)(void); typedef 18 FP f5(FP a, int b) { return a + b; } 19 FP f5_1(FP a, int b) { return (a += b); } 20 FP f6(int a, FP b) { return a + b; } 21 FP f6_1(int a, FP b) { return (a += b); } 22 FP f [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandPredSpillCode.cpp | 79 unsigned FP = MI->getOperand(0).getReg(); local 80 assert(FP == QTM.getRegisterInfo()->getFrameRegister() && 94 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1); 103 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); 117 addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2); 126 unsigned FP = MI->getOperand(1).getReg(); local 127 assert(FP == QTM.getRegisterInfo()->getFrameRegister() && 138 .addReg(FP) 148 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); 158 HEXAGON_RESERVED_REG_2).addReg(FP) [all...] |
/external/llvm/lib/MC/ |
H A D | MCSubtargetInfo.cpp | 29 const unsigned *FP, 37 ForwardingPaths = FP; 23 InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, const SubtargetFeatureKV *PF, const SubtargetFeatureKV *PD, const SubtargetInfoKV *ProcSched, const InstrStage *IS, const unsigned *OC, const unsigned *FP, unsigned NF, unsigned NP) argument
|
/external/openssl/crypto/des/ |
H A D | des_locl.h | 363 /* IP and FP 394 Thanks for hints from Richard Outerbridge - he told me IP&FP 414 #define FP(l,r) \ macro
|
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.cpp | 41 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; local 110 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO); 116 DstML = MachineLocation(FP); 130 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; local 143 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO); 200 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; local 204 MRI.setPhysRegUsed(FP); [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.cpp | 100 bool FP = hasFP(MF); local 168 if (FP) { 181 // Set the FP from the SP. 186 // Show FP is now valid. 220 bool FP = hasFP(MF); local 221 if (FP) { 245 if (FP) { 367 // A callee save register is used to hold the FP.
|
H A D | XCoreRegisterInfo.cpp | 208 bool FP = TFI->hasFP(MF); local 217 if (FP) {
|
/external/llvm/tools/bugpoint/ |
H A D | ExtractFunction.cpp | 248 Constant *FP = CS->getOperand(1); local 249 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(FP)) 251 FP = CE->getOperand(0); 252 if (Function *F = dyn_cast<Function>(FP)) {
|
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 151 // when the FP is not needed. 190 unsigned FP = TFI->hasFP(MF) ? 1 : 0; local 191 return 32 - FP - DefaultSafety; 536 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
|
H A D | PPCISelLowering.cpp | 177 // PowerPC wants to turn select_cc of FP into fsel when possible. 809 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 1688 /// GetFPR - Get the set of FP registers that should be allocated for arguments, 1918 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 2202 // All FP arguments reserve stack space in the Darwin ABI. 2504 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2505 // slot as the FP is never overwritten. 2549 // Load the LR and FP stack slot for later adjusting. 2556 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 2557 // slot as the FP i 3825 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); local 3860 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); local [all...] |
/external/llvm/lib/ExecutionEngine/ |
H A D | ExecutionEngine.cpp | 317 Constant *FP = CS->getOperand(1); local 318 if (FP->isNullValue()) 322 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(FP)) 324 FP = CE->getOperand(0); 327 if (Function *F = dyn_cast<Function>(FP))
|
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 297 unsigned FP = TFI->hasFP(MF) ? 1 : 0; local 298 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 316 // No FP, R9 is available. 328 // FP is R7, R9 is available. 340 // FP is R11, R9 is available. 352 // No FP, R9 is not available. 364 // FP is R7, R9 is not available. 376 // FP is R11, R9 is not available. 513 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 853 /// reference would be better served by a base register other than FP [all...] |
H A D | ARMFastISel.cpp | 510 // the combined constant into an FP reg. 1082 // load. Now we must move from the GRP to the FP register. 1588 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg); local 1589 if (FP == 0) return false; 1599 .addReg(FP));
|
/external/llvm/lib/VMCore/ |
H A D | PassManager.cpp | 272 FPPassManager *FP = static_cast<FPPassManager *>(PassManagers[N]); 273 return FP; 1422 FunctionPass *FP = getContainedPass(Index); local 1423 AnalysisResolver *AR = FP->getResolver(); 1466 FunctionPass *FP = getContainedPass(Index); local 1467 FP->dumpPassStructure(Offset + 1); 1468 dumpLastUses(FP, Offset+1); 1486 FunctionPass *FP = getContainedPass(Index); local 1489 dumpPassInfo(FP, EXECUTION_MSG, ON_FUNCTION_MSG, F.getName()); 1490 dumpRequiredSet(FP); [all...] |
/external/llvm/lib/Transforms/Vectorize/ |
H A D | BBVectorize.cpp | 2293 DenseMap<Value *, Value *>::iterator FP = ChosenPairs.find(P->second); local 2294 assert(FP != ChosenPairs.end() && "Flipped pair not found in list"); 2295 ChosenPairs.erase(FP);
|
/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 337 // SPU has a legal FP -> signed INT instruction for f32, but for f64, need 1101 ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode()); local 1103 assert((FP != 0) && 1106 uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble()); 1689 // NOTE: pretend the constant is an integer. LLVM won't load FP constants 1698 // NOTE: pretend the constant is an integer. LLVM won't load FP constants
|
/external/valgrind/main/massif/ |
H A D | ms_main.c | 889 NULL/*array to dump FP values in*/, 2132 #define FP(format, args...) ({ \ macro 2191 FP("%sn%d: %lu ", depth_str, sxpt->Sig.n_children, sxpt->szB); 2208 // Nb: We treat this specially (ie. we don't use FP) so that if the 2267 FP("%sn0: %lu in %d place%s below massif's threshold (%s)\n", 2282 FP("#-----------\n"); 2283 FP("snapshot=%d\n", snapshot_n); 2284 FP("#-----------\n"); 2285 FP("time=%lld\n", snapshot->time); 2286 FP("mem_heap_ [all...] |