Searched refs:Mask (Results 1 - 25 of 109) sorted by relevance

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/external/clang/include/clang/AST/
H A DDeclAccessPair.h32 enum { Mask = 0x3 }; enumerator in enum:clang::DeclAccessPair::__anon3263
42 return (NamedDecl*) (~Mask & (uintptr_t) Ptr);
45 return AccessSpecifier(Mask & (uintptr_t) Ptr);
H A DDeclGroup.h58 enum Kind { SingleDeclKind=0x0, DeclGroupKind=0x1, Mask=0x1 };
62 return (Kind) (reinterpret_cast<uintptr_t>(D) & Mask);
97 return *((DeclGroup*)(reinterpret_cast<uintptr_t>(D) & ~Mask));
H A DType.h161 Qualifiers() : Mask(0) {}
163 static Qualifiers fromFastMask(unsigned Mask) { argument
165 Qs.addFastQualifiers(Mask);
178 Qs.Mask = opaque;
184 return Mask;
187 bool hasConst() const { return Mask & Const; }
189 Mask = (Mask & ~Const) | (flag ? Const : 0);
191 void removeConst() { Mask &= ~Const; }
192 void addConst() { Mask |
428 uint32_t Mask; member in class:clang::Qualifiers
695 removeLocalFastQualifiers(unsigned Mask) argument
4660 removeLocalCVRQualifiers(unsigned Mask) argument
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/external/skia/src/svg/
H A DSkSVGMask.cpp21 DEFINE_SVG_INFO(Mask)
H A DSkSVGMask.h16 DECLARE_SVG_INFO(Mask);
/external/llvm/lib/Support/
H A DMemory.cpp57 const intptr_t Mask = ~(LineSize - 1);
58 const intptr_t StartLine = ((intptr_t) Addr) & Mask;
59 const intptr_t EndLine = ((intptr_t) Addr + Len + LineSize - 1) & Mask;
/external/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp28 // Mask manipulation functions.
35 static unsigned getMaskElt(unsigned Mask, unsigned Elt) { argument
36 return (Mask >> ((3-Elt)*4)) & 0xF;
39 static unsigned setMaskElt(unsigned Mask, unsigned Elt, unsigned NewVal) { argument
41 return (Mask & ~(0xF << FieldShift)) | (NewVal << FieldShift);
45 static bool isValidMask(unsigned short Mask) { argument
46 unsigned short UndefBits = Mask & 0x8888;
47 return (Mask & ((UndefBits >> 1)|(UndefBits>>2)|(UndefBits>>3))) == 0;
52 static bool hasUndefElements(unsigned short Mask) { argument
53 return (Mask
58 isOnlyLHSMask(unsigned short Mask) argument
73 getCompressedMask(unsigned short Mask) argument
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/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp210 SmallVectorImpl<Constant*> &Mask) {
216 Mask.assign(NumElts, UndefValue::get(Type::getInt32Ty(V->getContext())));
222 Mask.push_back(ConstantInt::get(Type::getInt32Ty(V->getContext()), i));
228 Mask.push_back(ConstantInt::get(Type::getInt32Ty(V->getContext()),
246 if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) {
248 Mask[InsertedIdx] = UndefValue::get(Type::getInt32Ty(V->getContext()));
261 if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) {
264 Mask[InsertedIdx % NumElts] =
269 Mask[InsertedIdx % NumElts] =
287 static Value *CollectShuffleElements(Value *V, SmallVectorImpl<Constant*> &Mask, argument
209 CollectSingleShuffleElements(Value *V, Value *LHS, Value *RHS, SmallVectorImpl<Constant*> &Mask) argument
387 SmallVector<Constant*, 16> Mask; local
413 SmallVector<int, 16> Mask = SVI.getShuffleMask(); local
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/external/llvm/include/llvm/ADT/
H A DSmallBitVector.h232 // Mask off previous bits.
459 /// setBitsInMask - Add '1' bits from Mask to this vector. Don't resize.
460 /// This computes "*this |= Mask".
461 void setBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) { argument
463 applyMask<true, false>(Mask, MaskWords);
465 getPointer()->setBitsInMask(Mask, MaskWords);
468 /// clearBitsInMask - Clear any bits in this vector that are set in Mask.
469 /// Don't resize. This computes "*this &= ~Mask".
470 void clearBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) { argument
472 applyMask<false, false>(Mask, MaskWord
479 setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) argument
488 clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) argument
497 applyMask(const uint32_t *Mask, unsigned MaskWords) argument
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H A DBitVector.h174 // Mask off previous bits.
270 BitWord Mask = 1L << (Idx % BITWORD_SIZE);
271 return (Bits[Idx / BITWORD_SIZE] & Mask) != 0;
432 /// setBitsInMask - Add '1' bits from Mask to this vector. Don't resize.
433 /// This computes "*this |= Mask".
434 void setBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
435 applyMask<true, false>(Mask, MaskWords);
438 /// clearBitsInMask - Clear any bits in this vector that are set in Mask.
439 /// Don't resize. This computes "*this &= ~Mask".
440 void clearBitsInMask(const uint32_t *Mask, unsigne
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/external/llvm/lib/Analysis/
H A DAliasAnalysis.cpp87 ModRefResult Mask = ModRef;
89 Mask = Ref;
113 if ((Mask & Mod) && pointsToConstantMemory(Loc))
114 Mask = ModRefResult(Mask & ~Mod);
117 if (!AA) return Mask;
121 return ModRefResult(AA->getModRefInfo(CS, Loc) & Mask);
139 AliasAnalysis::ModRefResult Mask = ModRef;
144 Mask = ModRefResult(Mask
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H A DValueTracking.cpp94 APInt Mask = APInt::getLowBitsSet(BitWidth, LHSKnownZeroOut); local
95 KnownZero |= KnownZero2 & Mask;
96 KnownOne |= KnownOne2 & Mask;
105 APInt Mask = APInt::getLowBitsSet(BitWidth, RHSKnownZeroOut); local
106 KnownZero |= LHSKnownZero & Mask;
107 KnownOne |= LHSKnownOne & Mask;
243 "V, Mask, KnownOne and KnownZero should have same BitWidth");
937 APInt Mask = APInt::getSignedMaxValue(BitWidth); local
941 if ((KnownOne & Mask) != 0)
946 if ((KnownOne & Mask) !
988 MaskedValueIsZero(Value *V, const APInt &Mask, const TargetData *TD, unsigned Depth) argument
1152 APInt Mask; local
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/external/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp194 unsigned Mask = 0, Pos = 3; local
208 Mask |= (NCC & 1) << Pos;
229 Mask |= (1 << Pos);
231 Mask |= (CC & 1) << 4;
232 MIB.addImm(Mask);
H A DThumb1RegisterInfo.cpp425 unsigned Mask = (1 << NumBits) - 1;
426 if (((Offset / Scale) & ~Mask) == 0) {
461 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
464 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
466 Offset = (Offset - Mask * Scale);
496 unsigned Mask = (1 << NumBits) - 1; variable
498 if ((unsigned)Offset <= Mask * Scale) {
513 Mask = (1 << NumBits) - 1;
521 ImmedOffset = ImmedOffset & Mask;
523 Offset &= ~(Mask * Scal
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/external/llvm/lib/Target/
H A DTargetRegisterInfo.cpp81 for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
82 unsigned Offset = CountTrailingZeros_32(Mask);
86 Mask >>= Offset;
139 // Mask out the reserved registers
/external/openssl/crypto/asn1/
H A Dcharmap.pl68 * Mask of various character properties
/external/llvm/lib/VMCore/
H A DConstantFold.h41 Constant *Mask);
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsAsmBackend.cpp133 uint64_t Mask = ((uint64_t)(-1) >> local
135 CurVal |= Value & Mask;
/external/webkit/Source/JavaScriptCore/tests/mozilla/ecma/Expressions/
H A D11.7.1.js38 7. Mask out all but the least significant 5 bits of Result(6), that is,
143 function Mask( b, n ) { function
214 add = Mask( add, 5 );
H A D11.7.2.js38 7. Mask out all but the least significant 5 bits of Result(6), that is,
157 function Mask( b, n ) { function
226 a = Mask( a, 5 );
H A D11.7.3.js39 7. Mask out all but the least significant 5 bits of Result(6), that is,
148 function Mask( b, n ) { function
228 a = Mask( a, 5 );
/external/libnfc-nxp/src/
H A DphFriNfc_NdefRecord.h115 #define PH_FRINFC_NDEFRECORD_FLAG_MASK ((uint8_t)0xF8) /** \internal To Mask the Flag Byte */
450 static uint8_t phFriNfc_NdefRecord_NdefFlag(uint8_t Flags,uint8_t Mask);
/external/llvm/include/llvm/Analysis/
H A DValueTracking.h29 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
31 /// bit sets. This code only analyzes bits in Mask, in order to short-circuit
62 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
63 /// this predicate to simplify operations downstream. Mask is known to be
71 bool MaskedValueIsZero(Value *V, const APInt &Mask,
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp449 SDValue Mask = Op.getOperand(0); local
453 assert(VT.isVector() && !Mask.getValueType().isVector()
478 Mask = DAG.getNode(ISD::SELECT, DL, BitTy, Mask,
483 SmallVector<SDValue, 8> Ops(NumElem, Mask);
484 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, &Ops[0], Ops.size());
494 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
496 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
508 SDValue Mask = Op.getOperand(0); local
536 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOne
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/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2549 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); local
2550 assert(Mask && "Missing call preserved mask for calling convention");
2551 Ops.push_back(DAG.getRegisterMask(Mask));
2649 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3199 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3202 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, argument
3205 if (!isUndefOrEqual(Mask[i], Low))
3213 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { argument
3215 return (Mask[0] < 4 && Mask[
3223 isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) argument
3252 isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) argument
3281 isPALIGNRMask(ArrayRef<int> Mask, EVT VT, const X86Subtarget *Subtarget) argument
3354 CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, unsigned NumElems) argument
3371 isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, bool Commuted = false) argument
3424 isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) argument
3443 isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) argument
3460 isMOVLPMask(ArrayRef<int> Mask, EVT VT) argument
3482 isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) argument
3551 isUNPCKLMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2, bool V2IsSplat = false) argument
3590 isUNPCKHMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2, bool V2IsSplat = false) argument
3628 isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) argument
3671 isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) argument
3703 isMOVLMask(ArrayRef<int> Mask, EVT VT) argument
3727 isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) argument
3787 isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) argument
3818 isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, bool V2IsSplat = false, bool V2IsUndef = false) argument
3842 isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, const X86Subtarget *Subtarget) argument
3865 isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, const X86Subtarget *Subtarget) argument
3888 isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) argument
3908 isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) argument
3979 unsigned Mask = 0; local
4001 unsigned Mask = 0; local
4025 unsigned Mask = 0; local
4108 unsigned Mask = 0; local
4153 ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) argument
4209 ShouldXformToMOVLP(SDNode *V1, SDNode *V2, ArrayRef<int> Mask, EVT VT) argument
4340 NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) argument
4353 SmallVector<int, 8> Mask; local
4364 SmallVector<int, 8> Mask; local
4376 SmallVector<int, 8> Mask; local
4493 getTargetShuffleMask(SDNode *N, MVT VT, SmallVectorImpl<int> &Mask, bool &IsUnary) argument
4923 SmallVector<int, 8> Mask; local
5166 SmallVector<int, 8> Mask; local
5318 SmallVector<int, 4> Mask; local
6169 SmallVector<int, 16> Mask; local
6868 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, local
7043 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; local
7062 int Mask[2] = { 1, -1 }; local
8220 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, local
8252 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, local
10753 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); local
10797 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); local
11794 isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, EVT VT) const argument
14237 unsigned Mask = 0; local
14509 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); local
14873 SDValue Mask = N1.getOperand(0); local
15471 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); local
15489 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); local
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